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authorSimon Glass <sjg@chromium.org>2026-08-03 08:10:23 -0600
committerLinus Walleij <linusw@kernel.org>2026-08-07 00:11:05 +0200
commit5b695c191cc85f0fd62eec885b55d01468dc9f2c (patch)
treee40ac3b2bd609aa49502eb467402063cff915c4b /tools/perf/scripts/python/flamegraph.py
parent27e5b8efc25b9238865288b7091ae6915c2f7c14 (diff)
pinctrl: rockchip: Reset the pin count when recalculating SoC data
rockchip_pinctrl_get_soc_data() mutates the static per-SoC data. The iomux and drive offsets are recalculated idempotently, since a rerun anchors at the values calculated before, but the total pin count only accumulates: each run adds every bank's pins again. When the probe is deferred and runs a second time, nr_pins doubles and every bank's pin_base shifts, so later pin lookups resolve to the wrong bank and the wrong registers. Reset the pin count at the start of the calculation, so that a rerun produces the same values. This is verified on a Luckfox Pico Mini B (RV1103, with the pending RV1106 series applied) by forcing the probe to defer once: without this patch the second probe calculates nr_pins=304 instead of 152 and no GPIO bank comes up; with it the recalculation matches the first run and all banks work. Fixes: d3e5116119bd ("pinctrl: add pinctrl driver for Rockchip SoCs") Link: https://sashiko.dev/#/patchset/20260729132736.3807082-1-sjg@chromium.org?part=4 Assisted-by: Claude:claude-opus-5 Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/flamegraph.py')
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