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| author | Shiji Yang <yangshiji66@outlook.com> | 2025-06-18 11:42:06 +0800 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2026-04-06 14:06:02 +0200 |
| commit | c2631cc4508c2e331759b0e5481a03d6b4b76346 (patch) | |
| tree | b9214e5ac4fd81721b795a72949449d0c9549ea1 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 3dbb08276836de58fc3097526c4bd9c3abe8f142 (diff) | |
mips: pci-mt7620: add more register init values
These missing register init values are ported from the vendor SDK.
It should have some stability enhancements. Tested on both MT7620
and MT7628.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions