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| author | Shiji Yang <yangshiji66@outlook.com> | 2025-06-18 11:42:05 +0800 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2026-04-06 14:05:58 +0200 |
| commit | 3dbb08276836de58fc3097526c4bd9c3abe8f142 (patch) | |
| tree | 692bdb756a6182278822c48a9fdd161b65cb3969 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | c7dd395d7b53a66de8503507fe7ef21b8fab3e57 (diff) | |
mips: pci-mt7620: fix bridge register access
Host bridge registers and PCI RC control registers have different
memory base. pcie_m32() is used to write the RC control registers
instead of bridge registers. This patch introduces bridge_m32()
and use it to operate bridge registers to fix the access issue.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions