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authorBiju Das <biju.das.jz@bp.renesas.com>2025-11-29 16:42:58 +0000
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2025-12-17 15:07:06 +0100
commit3a3ab10245b6779e32114bc70052ec7a8a380152 (patch)
treeeb6dbc12b17c300d377541fa80a359d2c6e4546c /rust/alloc/collections/git@git.tavy.me:linux.git
parent0774c43c006bf6e411514920cc57a42abe9374c1 (diff)
serial: sh-sci: Update rx_trigger size for RZ/T2H RSCI
The RZ/T2H RSCI has 16-stage FIFO. Like other SoCs, set the default rx_trigger as the fifosize. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/20251129164325.209213-3-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'rust/alloc/collections/git@git.tavy.me:linux.git')
0 files changed, 0 insertions, 0 deletions