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authorBiju Das <biju.das.jz@bp.renesas.com>2025-11-29 16:42:57 +0000
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2025-12-17 15:07:06 +0100
commit0774c43c006bf6e411514920cc57a42abe9374c1 (patch)
treec40b7ee6967d658691048de128c79e7a0f6b1dc8 /rust/alloc/collections/git@git.tavy.me:linux.git
parent695f986155d9dd95aef4acfca6dd31bf4b83282d (diff)
dt-bindings: serial: renesas,rsci: Document RZ/G3E support
Add documentation for the serial communication interface (RSCI) found on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets. It has 6 interrupts compared to 4 on RZ/T2H. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/20251129164325.209213-2-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'rust/alloc/collections/git@git.tavy.me:linux.git')
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