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authorDave Jiang <dave.jiang@intel.com>2026-06-04 11:01:54 -0700
committerDave Jiang <dave.jiang@intel.com>2026-06-04 16:01:01 -0700
commit26aa60e0276272ae61b843a05a91748dcb1130f9 (patch)
tree973b697c3411e61c7c506aaf15bf2b4f3128590f /drivers/phy/eswin/git@git.tavy.me:linux.git
parent66782cfa0085369e2d8c861042f7c6d43431bdb3 (diff)
cxl/pci: Convert PCIBIOS errors to errno on DVSEC config accesses
PCI config space accessors return positive PCIBIOS_* status codes on failure that are positive integers. Several DVSEC accesses in the CXL core propagated these raw values to callers that test for failure against less than 0. Thus silently misinterpret the return value as success. Convert the positive error values to negative errno values so the checks are correct on error paths. While the chances of a config access failure are low, fix for correctness and to avoid confusion in the future when more DVSEC accesses are added. Fixes: 14d788740774 ("cxl/mem: Consolidate CXL DVSEC Range enumeration in the core") Fixes: ce17ad0d5498 ("cxl: Wait Memory_Info_Valid before access memory related info") Reviewed-by: Richard Cheng <icheng@nvidia.com> Reviewed-by: Jonathan Cameron <jic23@kernel.org> Assisted-by: Claude:claude-opus-4-8 Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20260604180154.1925149-3-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'drivers/phy/eswin/git@git.tavy.me:linux.git')
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