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authorDave Jiang <dave.jiang@intel.com>2026-06-04 11:01:53 -0700
committerDave Jiang <dave.jiang@intel.com>2026-06-04 15:38:00 -0700
commit66782cfa0085369e2d8c861042f7c6d43431bdb3 (patch)
tree2e13aa9910f377533354208ccd3a89001a8d9014 /drivers/phy/eswin/git@git.tavy.me:linux.git
parente43ffb69e0438cddd72aaa30898b4dc446f664f8 (diff)
cxl/pci: Fix the incorrect check of pci_read_config_word() return
pci_read_config_word() returns PCIBIOS_* status on error which are positive values. The check should be for non-zero values to indicate error. Fix cxl_set_mem_enable() to check for non-zero return value instead of negative value. While fixing this, also convert the error to negative errno value when returning on error path. Fixes: 34e37b4c432c ("cxl/port: Enable HDM Capability after validating DVSEC Ranges") Reviewed-by: Richard Cheng <icheng@nvidia.com> Reviewed-by: Jonathan Cameron <jic23@kernel.org> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Assisted-by: Claude:claude-opus-4-8 Link: https://patch.msgid.link/20260604180154.1925149-2-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'drivers/phy/eswin/git@git.tavy.me:linux.git')
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