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authorSherry Sun <sherry.sun@nxp.com>2026-05-07 14:53:29 +0800
committerFrank Li <Frank.Li@nxp.com>2026-05-19 14:14:10 -0400
commitbb97f6f67cc9c7d82aaee7eee9b9c0273050264e (patch)
tree8e147b9112526615c3be7a7f00d3aceddb6c0eb5
parent0549cdb08a846babf44ea97a03d866dbcfc17873 (diff)
arm64: dts: imx95-15x15-evk: Disable PCIe bus in the default dts
Disable the PCIe bus in the default device tree to avoid shared regulator conflicts between SDIO and PCIe buses. The non-deterministic probe order between these two buses can break the PCIe initialization sequence, causing PCIe devices to fail detection intermittently. On i.MX95-15x15 EVK board, the M.2 connector is physically wired to both USDHC3 and PCIe0, however the out-of-box module is SDIO IW612 WiFi, so enable SDIO WiFi in the default imx95-15x15-evk.dts. Add 'm2_usdhc' label to USDHC3 to support device tree overlay for PCIe modules. Users who need PCIe can use imx95-15x15-evk-pcie.dtb (added in a follow-up patch) which applies an overlay to enable PCIe and disable USDHC3. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
-rw-r--r--arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
index 7eb12e7d5014..e4649d7f9122 100644
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
@@ -557,7 +557,7 @@
vpcie-supply = <&reg_m2_pwr>;
vpcie3v3aux-supply = <&reg_m2_pwr>;
supports-clkreq;
- status = "okay";
+ status = "disabled";
};
&pcie0_ep {
@@ -1137,7 +1137,7 @@
status = "okay";
};
-&usdhc3 {
+m2_usdhc: &usdhc3 {
bus-width = <4>;
keep-power-in-suspend;
mmc-pwrseq = <&usdhc3_pwrseq>;