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authorSherry Sun <sherry.sun@nxp.com>2026-05-07 14:53:28 +0800
committerFrank Li <Frank.Li@nxp.com>2026-05-19 14:14:09 -0400
commit0549cdb08a846babf44ea97a03d866dbcfc17873 (patch)
treead3ecf585e4d282827284da52ec7e72ee7f21d81
parent9a8f11f6f786f42b35c9b0944a2b87052d28cd48 (diff)
arm64: dts: imx8mp-evk: Disable PCIe bus in the default dts
Disable the PCIe bus in the default device tree to avoid shared regulator conflicts between SDIO and PCIe buses. The non-deterministic probe order between these two buses can break the PCIe initialization sequence, causing PCIe devices to fail detection intermittently. On i.MX8MP EVK board, the M.2 connector is physically wired to both USDHC1 and PCIe0, however the out-of-box module is SDIO IW612 WiFi, so enable the SDIO WiFi in the default imx8mp-evk.dts. Add 'm2_usdhc' label to USDHC1 to support device tree overlay for PCIe modules. Users who need PCIe can use imx8mp-evk-pcie.dtb (added in a follow-up patch) which applies an overlay to enable PCIe and disable USDHC1. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp-evk.dts4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index d0a2bd975a18..2feb5b18645c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -774,7 +774,7 @@
vpcie-supply = <&reg_pcie0>;
vpcie3v3aux-supply = <&reg_pcie0>;
supports-clkreq;
- status = "okay";
+ status = "disabled";
};
&pcie0_ep {
@@ -870,7 +870,7 @@
status = "okay";
};
-&usdhc1 {
+m2_usdhc: &usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;