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authorMarek Vasut <marek.vasut+renesas@mailbox.org>2026-01-15 03:39:43 +0100
committerLuca Ceresoli <luca.ceresoli@bootlin.com>2026-03-03 14:33:20 +0100
commitfca11428425e92bf21d4a7f5865708c5e64430e4 (patch)
tree5409106d3ad5ffa5925cf56146f38061fddfacad /tools/perf/scripts/python/stackcollapse.py
parent2befa6407d5c8b543be32c2276d396db395d9d02 (diff)
drm/bridge: waveshare-dsi: Add support for 1..4 DSI data lanes
Parse the data lane count out of DT. Limit the supported data lanes to 1..4 which is the maximum available DSI pairs on the connector of any known panels which may use this bridge. Internally, this bridge is an ChipOne ICN6211 which loads its register configuration from a dedicated storage and its I2C does not seem to be accessible. The ICN6211 also supports up to 4 DSI lanes, so this is a hard limit. To avoid any breakage on old DTs where the parsing of data lanes from DT may fail, fall back to the original hard-coded value of 2 lanes and warn user. The lane configuration is preconfigured in the bridge for each of the WaveShare panels. The 13.3" DSI panel works with 4-lane configuration, others seem to use 2-lane configuration. This is a hardware property, so the actual count should come from DT. Reviewed-by: Joseph Guo <qijian.guo@nxp.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://patch.msgid.link/20260115024004.660986-2-marek.vasut+renesas@mailbox.org Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
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