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| author | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2026-01-15 03:39:42 +0100 |
|---|---|---|
| committer | Luca Ceresoli <luca.ceresoli@bootlin.com> | 2026-03-03 14:33:20 +0100 |
| commit | 2befa6407d5c8b543be32c2276d396db395d9d02 (patch) | |
| tree | 4a645a8a86ee0178464e3e161f0f7bd1cbeee288 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 86a14330bf0598ce89177cebcc19e2cf810abf44 (diff) | |
dt-bindings: display: bridge: waveshare,dsi2dpi: Document 1..4 DSI lane support
Describe 1..4 DSI lanes as supported. Internally, this bridge is
an ChipOne ICN6211 which loads its register configuration from a
dedicated storage and its I2C does not seem to be accessible. The
ICN6211 supports up to 4 DSI lanes, so this is a hard limit for
this bridge. The lane configuration is preconfigured in the bridge
for each of the WaveShare panels.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260115024004.660986-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions