diff options
| author | John Madieu <john.madieu.xa@bp.renesas.com> | 2026-03-06 15:34:17 +0100 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2026-03-15 21:10:50 +0530 |
| commit | 1e75d2e9a0e018b53f06dcc2e9345ac10f1aa174 (patch) | |
| tree | e2ea75a4c3c32b4b0b87d95109606175484db487 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 5f2c4de717786150f8d6cdbdbffb986cd3c59edb (diff) | |
PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility
Program the class code register explicitly during PCIe configuration
initialization. RZ/G3E requires this register to be set, while RZ/G3S
has these values as hardware defaults.
This configuration is harmless for RZ/G3S where these match the hardware
defaults, and necessary for RZ/G3E to properly identify the device as a
PCI bridge.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # RZ/V2N EVK
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20260306143423.19562-11-john.madieu.xa@bp.renesas.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions