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| author | John Madieu <john.madieu.xa@bp.renesas.com> | 2026-03-06 15:34:16 +0100 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2026-03-15 21:08:41 +0530 |
| commit | 5f2c4de717786150f8d6cdbdbffb986cd3c59edb (patch) | |
| tree | 495f6e45f776190f073e2bf0bed0759cc412a9b1 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 4ec4ccdaace40397638c305c0a36b423d2142a93 (diff) | |
PCI: rzg3s-host: Add SoC-specific configuration and initialization callbacks
Add optional cfg_pre_init, cfg_post_init, and cfg_deinit callbacks
to handle SoC-specific configuration methods. While RZ/G3S uses the Linux
reset framework with dedicated reset lines, other SoC variants like RZ/G3E
control configuration resets through PCIe AXI registers.
As Linux reset bulk API gracefully handles optional NULL reset lines
(num_cfg_resets = 0 for RZ/G3E), the driver continues to use the standard
reset framework when reset lines are available, while custom callbacks
are only invoked when provided.
This provides a balanced pattern where:
- RZ/G3S: Uses callbacks that fall back to the reset framework
- RZ/G3E: Sets num_cfg_resets=0, provides
cfg_pre_init/cfg_post_init/cfg_deinit
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # RZ/V2N EVK
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20260306143423.19562-10-john.madieu.xa@bp.renesas.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
