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| author | Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> | 2026-04-08 12:36:51 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-04 14:03:08 +0200 |
| commit | 8a6ccb522858e196e0e89a602f4dd4624b7f6e7a (patch) | |
| tree | a19af9e8722bc1f2d764933e9e8d7407dc7600b0 /rust/zerocopy/src/pointer/git@git.tavy.me:linux-stable.git | |
| parent | 7a9e1c485ce8040a6fe1ac8712e57860fe486cb3 (diff) | |
clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK
Add support for the SMUX2_DSI0_CLK and SMUX2_DSI1_CLK clock muxes
present on the r9a09g047 SoC.
These muxes select between CDIV7_DSI{0,1}_CLK and CSDIV_2to16_PLLDSI{0,1}
using the CPG_SSEL3 register (SELCTL0 and SELCTL1 bits).
According to the hardware manual, when LVDS0 or LVDS1 outputs are used,
SELCTL0 or SELCTL1 must be set accordingly.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/9595f56ce8ab120477bfc11eaafb0f2b655d049a.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'rust/zerocopy/src/pointer/git@git.tavy.me:linux-stable.git')
0 files changed, 0 insertions, 0 deletions