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| author | Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> | 2026-04-08 12:36:50 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-04 14:03:08 +0200 |
| commit | 7a9e1c485ce8040a6fe1ac8712e57860fe486cb3 (patch) | |
| tree | b649d92efb9ed003cbb11f65764ad101e27c3709 /rust/zerocopy/src/pointer/git@git.tavy.me:linux-stable.git | |
| parent | 0e1597c688880c2b916401c88afcd476a4e912a2 (diff) | |
clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks
Add the CLK_PLLDSI0_CSDIV and CLK_PLLDSI1_CSDIV fixed-factor clocks to
the r9a09g047 SoC clock driver.
These clocks are required to enable DSI and RGB output support.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/4d5b4ddad89770447b3818381d5353f5065b72b5.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'rust/zerocopy/src/pointer/git@git.tavy.me:linux-stable.git')
0 files changed, 0 insertions, 0 deletions