diff options
| author | Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> | 2026-04-08 12:36:49 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-04 14:03:08 +0200 |
| commit | 0e1597c688880c2b916401c88afcd476a4e912a2 (patch) | |
| tree | 1aad9c25a63173696b72fba15909a70984c1be96 /rust/zerocopy/src/pointer/git@git.tavy.me:linux-stable.git | |
| parent | 6913a6159688edee07185a6ed0f1c4ad57c881e5 (diff) | |
clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks
Add the CLK_PLLDSI0_DIV7 and CLK_PLLDSI1_DIV7 fixed-factor clocks to
the r9a09g047 SoC clock driver.
These clocks are required to enable LVDS0 and LVDS1 output support.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/e50c1721e1dc160e8b4518e8c5172f10cba4b58b.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'rust/zerocopy/src/pointer/git@git.tavy.me:linux-stable.git')
0 files changed, 0 insertions, 0 deletions