1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright 2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _DMUB_DCN42_H_
#define _DMUB_DCN42_H_
#include "dmub_dcn35.h"
#include "dmub_dcn401.h"
struct dmub_srv;
/* DCN42 register definitions. */
#define DMUB_DCN42_REGS() \
DMUB_SR(DMCUB_CNTL) \
DMUB_SR(DMCUB_CNTL2) \
DMUB_SR(DMCUB_SEC_CNTL) \
DMUB_SR(DMCUB_INBOX0_SIZE) \
DMUB_SR(DMCUB_INBOX0_RPTR) \
DMUB_SR(DMCUB_INBOX0_WPTR) \
DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
DMUB_SR(DMCUB_INBOX1_SIZE) \
DMUB_SR(DMCUB_INBOX1_RPTR) \
DMUB_SR(DMCUB_INBOX1_WPTR) \
DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
DMUB_SR(DMCUB_OUTBOX0_SIZE) \
DMUB_SR(DMCUB_OUTBOX0_RPTR) \
DMUB_SR(DMCUB_OUTBOX0_WPTR) \
DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
DMUB_SR(DMCUB_OUTBOX1_SIZE) \
DMUB_SR(DMCUB_OUTBOX1_RPTR) \
DMUB_SR(DMCUB_OUTBOX1_WPTR) \
DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION4_OFFSET) \
DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION5_OFFSET) \
DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
DMUB_SR(DMCUB_REGION6_OFFSET) \
DMUB_SR(DMCUB_REGION6_OFFSET_HIGH) \
DMUB_SR(DMCUB_REGION6_TOP_ADDRESS) \
DMUB_SR(DMCUB_SCRATCH0) \
DMUB_SR(DMCUB_SCRATCH1) \
DMUB_SR(DMCUB_SCRATCH2) \
DMUB_SR(DMCUB_SCRATCH3) \
DMUB_SR(DMCUB_SCRATCH4) \
DMUB_SR(DMCUB_SCRATCH5) \
DMUB_SR(DMCUB_SCRATCH6) \
DMUB_SR(DMCUB_SCRATCH7) \
DMUB_SR(DMCUB_SCRATCH8) \
DMUB_SR(DMCUB_SCRATCH9) \
DMUB_SR(DMCUB_SCRATCH10) \
DMUB_SR(DMCUB_SCRATCH11) \
DMUB_SR(DMCUB_SCRATCH12) \
DMUB_SR(DMCUB_SCRATCH13) \
DMUB_SR(DMCUB_SCRATCH14) \
DMUB_SR(DMCUB_SCRATCH15) \
DMUB_SR(DMCUB_SCRATCH16) \
DMUB_SR(DMCUB_SCRATCH17) \
DMUB_SR(DMCUB_SCRATCH18) \
DMUB_SR(DMCUB_SCRATCH19) \
DMUB_SR(DMCUB_SCRATCH20) \
DMUB_SR(DMCUB_SCRATCH21) \
DMUB_SR(DMCUB_GPINT_DATAIN0) \
DMUB_SR(DMCUB_GPINT_DATAIN1) \
DMUB_SR(DMCUB_GPINT_DATAOUT) \
DMUB_SR(MMHUBBUB_SOFT_RESET) \
DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
DMUB_SR(DCN_VM_FB_OFFSET) \
DMUB_SR(DMCUB_TIMER_CURRENT) \
DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \
DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
DMUB_SR(DMCUB_INTERRUPT_ACK) \
DMUB_SR(DMU_CLK_CNTL) \
DMUB_SR(DMCUB_INTERRUPT_STATUS) \
DMUB_SR(DMCUB_REG_INBOX0_RDY) \
DMUB_SR(DMCUB_REG_INBOX0_MSG0) \
DMUB_SR(DMCUB_REG_INBOX0_MSG1) \
DMUB_SR(DMCUB_REG_INBOX0_MSG2) \
DMUB_SR(DMCUB_REG_INBOX0_MSG3) \
DMUB_SR(DMCUB_REG_INBOX0_MSG4) \
DMUB_SR(DMCUB_REG_INBOX0_MSG5) \
DMUB_SR(DMCUB_REG_INBOX0_MSG6) \
DMUB_SR(DMCUB_REG_INBOX0_MSG7) \
DMUB_SR(DMCUB_REG_INBOX0_MSG8) \
DMUB_SR(DMCUB_REG_INBOX0_MSG9) \
DMUB_SR(DMCUB_REG_INBOX0_MSG10) \
DMUB_SR(DMCUB_REG_INBOX0_MSG11) \
DMUB_SR(DMCUB_REG_INBOX0_MSG12) \
DMUB_SR(DMCUB_REG_INBOX0_MSG13) \
DMUB_SR(DMCUB_REG_INBOX0_MSG14) \
DMUB_SR(DMCUB_REG_INBOX0_RSP) \
DMUB_SR(DMCUB_REG_OUTBOX0_RDY) \
DMUB_SR(DMCUB_REG_OUTBOX0_MSG0) \
DMUB_SR(DMCUB_REG_OUTBOX0_RSP) \
DMUB_SR(HOST_INTERRUPT_CSR)
#define DMUB_DCN42_FIELDS() \
DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_ENABLE) \
DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \
DMUB_SF(DMCUB_REGION3_TMR_AXI_SPACE, DMCUB_REGION3_TMR_AXI_SPACE) \
DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \
DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) \
DMUB_SF(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS) \
DMUB_SF(DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE) \
DMUB_SF(DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE) \
DMUB_SF(DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE) \
DMUB_SF(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT) \
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK) \
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT) \
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN) \
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK) \
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT) \
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN)
struct dmub_srv_dcn42_reg_offset {
#define DMUB_SR(reg) uint32_t reg;
DMUB_DCN42_REGS()
DMCUB_INTERNAL_REGS()
#undef DMUB_SR
};
struct dmub_srv_dcn42_reg_shift {
#define DMUB_SF(reg, field) uint8_t reg##__##field;
DMUB_DCN42_FIELDS()
#undef DMUB_SF
};
struct dmub_srv_dcn42_reg_mask {
#define DMUB_SF(reg, field) uint32_t reg##__##field;
DMUB_DCN42_FIELDS()
#undef DMUB_SF
};
struct dmub_srv_dcn42_regs {
struct dmub_srv_dcn42_reg_offset offset;
struct dmub_srv_dcn42_reg_mask mask;
struct dmub_srv_dcn42_reg_shift shift;
};
/* Function declarations */
/* Initialization and configuration */
void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);
void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub);
/* Reset and control */
void dmub_dcn42_reset(struct dmub_srv *dmub);
void dmub_dcn42_reset_release(struct dmub_srv *dmub);
/* Firmware loading */
void dmub_dcn42_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1);
void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1);
void dmub_dcn42_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6);
/* Mailbox operations - Inbox1 */
void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub, const struct dmub_region *inbox1);
uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub);
uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub);
void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
/* Mailbox operations - Outbox1 */
void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub, const struct dmub_region *outbox1);
uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub);
void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
/* Mailbox operations - Outbox0 */
void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub, const struct dmub_region *outbox0);
uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub);
void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
/* Mailbox operations - Inbox0 */
void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub);
uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub);
/* REG Inbox0/Outbox0 operations */
void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);
uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub);
void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);
void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);
void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);
void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable);
void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub);
void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg);
void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp);
uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub);
void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable);
uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub);
/* GPINT operations */
void dmub_dcn42_set_gpint(struct dmub_srv *dmub, union dmub_gpint_data_register reg);
bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub, union dmub_gpint_data_register reg);
uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub);
uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub);
/* Status and detection */
bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub);
bool dmub_dcn42_is_supported(struct dmub_srv *dmub);
bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub);
bool dmub_dcn42_should_detect(struct dmub_srv *dmub);
/* Firmware boot status and options */
union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub);
union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub);
/* Timing and diagnostics */
uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub);
void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub);
bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub);
#endif /* _DMUB_DCN42_H_ */
|
