blob: e30cc461542b44b07edfed1cf0d658994ba9d847 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/ti,vip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments DRA7x Video Input Port (VIP)
maintainers:
- Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
description: |-
Video Input Port (VIP) can be found on devices such as DRA7xx and
provides the system interface and the processing capability to
connect parallel image-sensor as well as BT.656/1120 capable encoder
chip to DRA7x device.
Each VIP instance supports 2 independently configurable external
video input capture slices (Slice 0 and Slice 1) each providing
up to two video input ports (Port A and Port B).
properties:
compatible:
enum:
- ti,dra7-vip
reg:
maxItems: 1
interrupts:
items:
- description: IRQ index 0 is used for Slice0 interrupts
- description: IRQ index 1 is used for Slice1 interrupts
ti,ctrl-module:
description:
Reference to the device control module that provides clock-edge
inversion control for VIP ports. These controls allow the
VIP to sample pixel data on the correct clock edge.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle to device control module
- description: offset to the CTRL_CORE_SMA_SW_1 register
- description: Bit field to slice 0 port A
- description: Bit field to slice 0 port B
- description: Bit field to slice 1 port A
- description: Bit field to slice 1 port B
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port@[0-3]$':
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: |
Each VIP instance supports 2 independently configurable external video
input capture slices (Slice 0 and Slice 1) each providing up to two video
input ports (Port A and Port B). These ports represent the following
port@0 -> Slice 0 Port A
port@1 -> Slice 0 Port B
port@2 -> Slice 1 Port A
port@3 -> Slice 1 Port B
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
bus-width:
enum: [8, 16, 24]
default: 8
required:
- compatible
- reg
- interrupts
- ti,ctrl-module
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
video@48970000 {
compatible = "ti,dra7-vip";
reg = <0x48970000 0x1000>;
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
ti,ctrl-module = <&scm_conf 0x534 0x0 0x2 0x1 0x3>;
ports {
#address-cells = <1>;
#size-cells = <0>;
vin1a: port@0 {
reg = <0>;
vin1a_ep: endpoint {
remote-endpoint = <&camera1>;
hsync-active = <1>;
vsync-active = <1>;
pclk-sample = <0>;
bus-width = <8>;
};
};
vin1b: port@1 {
reg = <1>;
vin1b_ep: endpoint {
remote-endpoint = <&camera2>;
hsync-active = <1>;
vsync-active = <1>;
pclk-sample = <0>;
bus-width = <8>;
};
};
vin2a: port@2 {
reg = <2>;
vin2a_ep: endpoint {
remote-endpoint = <&camera3>;
hsync-active = <1>;
vsync-active = <1>;
pclk-sample = <0>;
bus-width = <16>;
};
};
vin2b: port@3 {
reg = <3>;
vin2b_ep: endpoint {
remote-endpoint = <&camera4>;
hsync-active = <1>;
vsync-active = <1>;
pclk-sample = <0>;
bus-width = <8>;
};
};
};
};
...
|
