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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,shikra-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Global Clock & Reset Controller on Qualcomm Shikra SoC
maintainers:
- Imran Shaik <imran.shaik@oss.qualcomm.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Global clock control module provides the clocks, resets and power
domains on Qualcomm Shikra SoC platform.
See also: include/dt-bindings/clock/qcom,shikra-gcc.h
properties:
compatible:
const: qcom,shikra-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: EMAC0 sgmiiphy mac rclk source
- description: EMAC0 sgmiiphy mac tclk source
- description: EMAC1 sgmiiphy mac rclk source
- description: EMAC1 sgmiiphy mac tclk source
- description: PCIE Pipe clock source
- description: USB3 phy wrapper pipe clock source
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@1400000 {
compatible = "qcom,shikra-gcc";
reg = <0x01400000 0x1f0000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<&emac0_sgmiiphy_rclk>,
<&emac0_sgmiiphy_tclk>,
<&emac1_sgmiiphy_rclk>,
<&emac1_sgmiiphy_tclk>,
<&pcie_pipe_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
power-domains = <&rpmpd RPMPD_VDDCX>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...
|
