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path: root/drivers
AgeCommit message (Expand)Author
2025-11-19interconnect: qcom: icc-rpmh: Get parent's regmap for nested NoCsLuca Weiss
2025-11-19Merge branch 'icc-dynamic-ids' into icc-nextGeorgi Djakov
2025-11-19gpio: elkhartlake: Convert to auxiliary driverRaag Jadav
2025-11-19platform/x86/intel: Introduce Intel Elkhart Lake PSE I/ORaag Jadav
2025-11-19ACPI: APEI: EINJ: Fix EINJV2 initialization and injectionTony Luck
2025-11-19regulator: make the subsystem aware of shared GPIOsBartosz Golaszewski
2025-11-19drm/i915/cx0: Enable dpll framework for MTL+Mika Kahola
2025-11-19drm/i915/cx0: Add MTL+ Thunderbolt PLL hooksImre Deak
2025-11-19drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLsMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDIMika Kahola
2025-11-19drm/i915/cx0: PLL verify debug state printImre Deak
2025-11-19drm/i915/cx0: Add MTL+ .crtc_get_dpll hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_freq hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Add .compare_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .dump_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .update_active_dpll hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .put_dplls hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_dplls hookMika Kahola
2025-11-19scsi: snic: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/i915/cx0: Compute plls for MTL+ platformMika Kahola
2025-11-19scsi: fnic: Switch to use %ptSpAndy Shevchenko
2025-11-19s390/dasd: Switch to use %ptSpAndy Shevchenko
2025-11-19ptp: ocp: Switch to use %ptSpAndy Shevchenko
2025-11-19pps: Switch to use %ptSpAndy Shevchenko
2025-11-19PCI: epf-test: Switch to use %ptSpAndy Shevchenko
2025-11-19net: dsa: sja1105: Switch to use %ptSpAndy Shevchenko
2025-11-19mmc: mmc_test: Switch to use %ptSpAndy Shevchenko
2025-11-19media: av7110: Switch to use %ptSpAndy Shevchenko
2025-11-19ipmi: Switch to use %ptSpAndy Shevchenko
2025-11-19igb: Switch to use %ptSpAndy Shevchenko
2025-11-19e1000e: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/xe: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/vblank: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/i915/cx0: Update C10/C20 state calculationMika Kahola
2025-11-19drm/i915/cx0: Add PLL information for MTL+Mika Kahola
2025-11-19drm/i915/cx0: Remove state verificationMika Kahola
2025-11-19drm/i915/cx0: Print additional Cx0 PLL HW stateImre Deak
2025-11-19drm/i915/cx0: Zero Cx0 PLL state before compute and HW readoutImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL port clock from PLL stateImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL DP mode from PLL stateImre Deak
2025-11-19drm/i915/cx0: Read out the Cx0 PHY SSC enabled stateImre Deak
2025-11-19drm/i915/cx0: Sanitize C10 PHY PLL SSC register setupImre Deak
2025-11-19drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Add macro to get DDI port width from a register valueImre Deak
2025-11-19drm/i915/cx0: Move definition of Cx0 PHY functions earlierImre Deak
2025-11-19drm/i915/cx0: Track the C20 PHY VDR state in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Sanitize calculating C20 PLL state from tablesImre Deak
2025-11-19drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flagImre Deak
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