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2026-08-19Merge tag 'pmdomain-v7.3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm Pull pmdomain updates from Ulf Hansson: - amlogic: Add support for A9 power domains - bcm: Raise ASB poll timeout to 100us for bcm2835-power - imx: Allow building power domain drivers as a modules - mediatek: - Add support for the MT6858 power domains - Add support for the MT8196 HFRP DirectCTL power domains - qcom: - Add support for RPMh power domains for Maili - Skip retention by default for rpmhpd - renesas: Add support for R-Car X5H Module Controller - rockchip: Add a regulator to the RK3568 NPU power domain - tegra: Add support for multi-socket platforms * tag 'pmdomain-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (24 commits) pmdomain: renesas: Add R-Car X5H MDLC driver dt-bindings: power: Document Renesas R-Car X5H Module Controller pmdomain: amlogic: Add support for A9 power domains controller dt-bindings: power: Add Amlogic A9 power domains clk: imx: imx8qxp: add soft dependency on SCU power domain driver pmdomain: imx: scu-pd: allow building as a module of: export of_stdout symbol pmdomain: imx8m{p,}-blk-ctrl: Add MODULE_DESCRIPTION pmdomain: mediatek: Add support for MT6858 SoC pmdomain: mediatek: Add support for secure modem power domain control dt-bindings: power: Add MediaTek MT6858 power domain controller pmdomain: rockchip: Add a regulator to the RK3568 NPU power domain pmdomain: imx: Make IMX8M/IMX9 BLK_CTRL tristate dt-bindings: power: qcom,rpmpd: document RPMh power domain for Maili pmdomain: tegra: Add support for multi-socket platforms pmdomain: bcm: bcm2835-power: Raise ASB poll timeout to 100us pmdomain: mediatek: Add support for MT8196 HFRP DirectCTL domains pmdomain: mediatek: Add support for Direct CTL simple power sequence pmdomain: mediatek: Respect PD relationships during error cleanup dt-bindings: power: mediatek: Add support for MT8196 direct HFRP ...
2026-08-12pmdomain: renesas: Add R-Car X5H MDLC driverGeert Uytterhoeven
Add a minimal Module Controller driver for the R-Car X5H (R8A78000) SoC. For now this just supports the always-on power domains, and dummy module clocks and resets for the serial console (which is enabled by the boot loader). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-07-24Merge tag 'renesas-drivers-for-v7.3-tag1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers Renesas driver updates for v7.3 - Drop duplicate default for ARCH_R8A78000. * tag 'renesas-drivers-for-v7.3-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: r8a78000: Drop duplicate "default ARCH_RENESAS" Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-07-16soc: renesas: r8a78000: Drop duplicate "default ARCH_RENESAS"Geert Uytterhoeven
The Kconfig entry for ARCH_R8A78000 contains both "default y if ARCH_RENESAS" and "default ARCH_RENESAS", which are sort-of duplicates. Drop the latter, to restore consistency with the other ARM64 entries. Fixes: 5284d0b09d1bdc69 ("soc: renesas: Identify R-Car X5H") Reported-by: Marek Vasut <marek.vasut@mailbox.org> Closes: https://lore.kernel.org/a069d50d-030d-4189-ae9d-37f989829da4@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Link: https://patch.msgid.link/64de6e95719a6dec7412cf7e917a42749e738b99.1783593775.git.geert+renesas@glider.be
2026-07-03Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c ↵Uwe Kleine-König (The Capable Hub)
files) Replace the #include of <linux/mod_devicetable.h> by the more specific <linux/device-id/*.h> where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich <dakr@kernel.org> Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
2026-05-29soc: renesas: rcar-mfis: Add R-Car V4H/V4M supportWolfram Sang
The above SoCs have a weird register layout for the mailbox registers. So, encapsulate register offset calculation in a per-SoC callback. Other than that, only a separate config struct and compatibles are needed. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260519075620.4128-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-25soc: renesas: Identify R-Car R8A779MD M3Le SoCMarek Vasut
Add support for identifying the R-Car M3Le (R8A779MD) SoC. The Renesas R-Car R8A779MD M3Le SoC is a variant of the already supported R-Car M3-N SoC with reduced peripherals. Enable support for the M3Le SoC through already existing ARCH_R8A77965 configuration symbol. PRR reads 0x67c05501. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20260504144534.43745-6-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-11soc: renesas: Convert to of_machine_get_match()Geert Uytterhoeven
Use the of_machine_get_match() helper to avoid accessing of_root directly, which is planned to become private. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://patch.msgid.link/10876b30a8bdb7d1cfcc2f23fb859f2ffea335fe.1772468323.git.geert+renesas@glider.be
2026-05-04soc: renesas: Add R-Car X5H PRR supportWolfram Sang
On R-Car X5H, PRR is inside the MFIS memory block, so we need to access it similar to e.g. RZ/G2L. Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260402112709.13002-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-04soc: renesas: Add Renesas R-Car MFIS driverWolfram Sang
Renesas R-Car MFIS offers multiple features but most importantly mailboxes and hwspinlocks. Because they share a common register space and a common register unprotection mechanism, a single driver was chosen to handle all dependencies. (MFD and auxiliary bus have been tried as well, but they failed because of circular dependencies.) In this first step, the driver implements common register access and a mailbox controller. hwspinlock support will be added incrementally, once the subsystem allows out-of-directory drivers. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260402112709.13002-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27soc: renesas: r9a09g057-sys: Move common code to a helperClaudiu Beznea
Move common code from rzv2h_regmap_{readable,writeable}_reg() to a helper and use it to avoid code duplication. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260403141341.2851926-6-claudiu.beznea.uj@bp.reneasas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27soc: renesas: r9a09g056-sys: Move common code to a helperClaudiu Beznea
Move common code from rzv2n_regmap_{readable,writeable}_reg() to a helper and use it to avoid code duplication. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260403141341.2851926-5-claudiu.beznea.uj@bp.reneasas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27soc: renesas: r9a09g047-sys: Move common code to a helperClaudiu Beznea
Move common code from rzg3e_regmap_{readable,writeable}_reg() to a helper and use it to avoid code duplication. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260403141341.2851926-4-claudiu.beznea.uj@bp.reneasas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27soc: renesas: r9a08g046-sysc: Move common code to a helperClaudiu Beznea
Move common code from rzg3l_regmap_{readable,writeable}_reg() to a helper and use it to avoid code duplication. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260403141341.2851926-3-claudiu.beznea.uj@bp.reneasas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27soc: renesas: r9a08g045-sysc: Move common code to a helperClaudiu Beznea
Move common code from rzg3s_regmap_{readable,writeable}_reg() to a helper and use it to avoid code duplication. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260403141341.2851926-2-claudiu.beznea.uj@bp.reneasas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-16soc: renesas: r9a09g056-sys: Mark rzv2n_sys_init_data as __initconstLad Prabhakar
Annotate rzv2n_sys_init_data with __initconst as it is only used during initialization. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260309165946.3003731-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-16soc: renesas: r9a09g047-sys: Mark rzg3e_sys_init_data as __initconstLad Prabhakar
Annotate rzg3e_sys_init_data with __initconst as it is only used during initialization. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260309165946.3003731-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-16soc: renesas: r9a09g057-sys: Mark rzv2h_sys_init_data as __initconstLad Prabhakar
Annotate rzv2h_sys_init_data with __initconst as it is only used during initialization. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260309165946.3003731-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-06soc: renesas: rz-sysc: Add SoC identification for RZ/G3L SoCBiju Das
Add SoC identification for the RZ/G3L SoC using the System Controller (SYSC) block. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203103031.247435-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-02-21Convert more 'alloc_obj' cases to default GFP_KERNEL argumentsLinus Torvalds
This converts some of the visually simpler cases that have been split over multiple lines. I only did the ones that are easy to verify the resulting diff by having just that final GFP_KERNEL argument on the next line. Somebody should probably do a proper coccinelle script for this, but for me the trivial script actually resulted in an assertion failure in the middle of the script. I probably had made it a bit _too_ trivial. So after fighting that far a while I decided to just do some of the syntactically simpler cases with variations of the previous 'sed' scripts. The more syntactically complex multi-line cases would mostly really want whitespace cleanup anyway. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2026-02-21Convert 'alloc_obj' family to use the new default GFP_KERNEL argumentLinus Torvalds
This was done entirely with mindless brute force, using git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' | xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/' to convert the new alloc_obj() users that had a simple GFP_KERNEL argument to just drop that argument. Note that due to the extreme simplicity of the scripting, any slightly more complex cases spread over multiple lines would not be triggered: they definitely exist, but this covers the vast bulk of the cases, and the resulting diff is also then easier to check automatically. For the same reason the 'flex' versions will be done as a separate conversion. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2026-02-21treewide: Replace kmalloc with kmalloc_obj for non-scalar typesKees Cook
This is the result of running the Coccinelle script from scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to avoid scalar types (which need careful case-by-case checking), and instead replace kmalloc-family calls that allocate struct or union object instances: Single allocations: kmalloc(sizeof(TYPE), ...) are replaced with: kmalloc_obj(TYPE, ...) Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...) are replaced with: kmalloc_objs(TYPE, COUNT, ...) Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...) are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...) (where TYPE may also be *VAR) The resulting allocations no longer return "void *", instead returning "TYPE *". Signed-off-by: Kees Cook <kees@kernel.org>
2026-02-10Merge tag 'soc-drivers-7.0' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "There are are a number of to firmware drivers, in particular the TEE subsystem: - a bus callback for TEE firmware that device drivers can register to - sysfs support for tee firmware information - minor updates to platform specific TEE drivers for AMD, NXP, Qualcomm and the generic optee driver - ARM SCMI firmware refactoring to improve the protocol discover among other fixes and cleanups - ARM FF-A firmware interoperability improvements The reset controller and memory controller subsystems gain support for additional hardware platforms from Mediatek, Renesas, NXP, Canaan and SpacemiT. Most of the other changes are for random drivers/soc code. Among a number of cleanups and newly added hardware support, including: - Mediatek MT8196 DVFS power management and mailbox support - Qualcomm SCM firmware and MDT loader refactoring, as part of the new Glymur platform support. - NXP i.MX9 System Manager firmware support for accessing the syslog - Minor updates for TI, Renesas, Samsung, Apple, Marvell and AMD SoCs" * tag 'soc-drivers-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (171 commits) bus: fsl-mc: fix an error handling in fsl_mc_device_add() reset: spacemit: Add SpacemiT K3 reset driver reset: spacemit: Extract common K1 reset code reset: Create subdirectory for SpacemiT drivers dt-bindings: soc: spacemit: Add K3 reset support and IDs reset: canaan: k230: drop OF dependency and enable by default reset: rzg2l-usbphy-ctrl: Add suspend/resume support reset: rzg2l-usbphy-ctrl: Propagate the return value of regmap_field_update_bits() reset: gpio: check the return value of gpiod_set_value_cansleep() reset: imx8mp-audiomix: Support i.MX8ULP SIM LPAV reset: imx8mp-audiomix: Extend the driver usage reset: imx8mp-audiomix: Switch to using regmap API reset: imx8mp-audiomix: Drop unneeded macros soc: fsl: qe: qe_ports_ic: Consolidate chained IRQ handler install/remove soc: mediatek: mtk-cmdq: Add mminfra_offset adjustment for DRAM addresses soc: mediatek: mtk-cmdq: Extend cmdq_pkt_write API for SoCs without subsys ID soc: mediatek: mtk-cmdq: Add pa_base parsing for hardware without subsys ID support soc: mediatek: mtk-cmdq: Add cmdq_get_mbox_priv() in cmdq_pkt_create() mailbox: mtk-cmdq: Add driver data to support for MT8196 mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction ...
2026-02-10Merge tag 'irq-drivers-2026-02-09' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq chip driver updates from Thomas Gleixner: - Add support for the Renesas RZ/V2N SoC - Add a new driver for the Renesas RZ/[TN]2H SoCs - Preserve the register state of the RISCV APLIC interrupt controller accross suspend/resume - Reinitialize the RISCV IMSIC registers after suspend/resume - Make the various Loongson interrupt chip drivers 32/64-bit aware - Handle the number of hardware interrupts in the SIFIVE PLIC driver correctly The hardware interrupt 0 is reserved which resulted in inconsistent accounting. That went unnoticed as the off by one is only noticable when the number of device interrupts is a multiple of 32 - The usual device tree updates, cleanups and improvements all over the place * tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits) irqchip/gic-v5: Fix spelling mistake "ouside" -> "outside" dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in PLIC irqchip/sifive-plic: Handle number of hardware interrupts correctly irqchip/aspeed-scu-ic: Remove unused variable mask irqchip/ti-sci-intr: Allow parsing interrupt-types per-line dt-bindings: interrupt-controller: ti,sci-intr: Per-line interrupt-types irqchip/renesas-rzv2h: Add suspend/resume support irqchip/aslint-sswi: Fix error check of of_io_request_and_map() result irqchip: Allow LoongArch irqchip drivers on both 32BIT/64BIT irqchip/loongson-pch-pic: Adjust irqchip driver for 32BIT/64BIT irqchip/loongson-pch-msi: Adjust irqchip driver for 32BIT/64BIT irqchip/loongson-htvec: Adjust irqchip driver for 32BIT/64BIT irqchip/loongson-eiointc: Adjust irqchip driver for 32BIT/64BIT irqchip/loongson-liointc: Adjust irqchip driver for 32BIT/64BIT irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT irqchip/riscv-aplic: Preserve APLIC states across suspend/resume irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit arm64: dts: renesas: r9a09g087: Add ICU support arm64: dts: renesas: r9a09g077: Add ICU support irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver ...
2026-01-15soc: renesas: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMAJonathan Cameron
The Kconfig menu entry was converted to a menuconfig to allow it to be hidden for !CONFIG_RISCV. The drivers under this new option were selected by some other Kconfig symbols and so an extra select CACHEMAINT_FOR_DMA is needed. Fixes: 4d1608d0ab33 ("cache: Make top level Kconfig menu a boolean dependent on RISCV") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202512100411.WxJU2No9-lkp@intel.com/ Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251210160047.201379-3-Jonathan.Cameron@huawei.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-15soc: renesas: Add support for RZ/N1 GPIO Interrupt MultiplexerHerve Codina (Schneider Electric)
On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines. Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260114093938.1089936-8-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-12-23soc: renesas: Enable ICU support on RZ/N2HCosmin Tanislav
The Renesas RZ/N2H (R9A09G087) SoC has the same Interrupt Controller (ICU) as the Renesas RZ/T2H (R9A09G077) SoC. Enable support for it by selecting the RENESAS_RZT2H_ICU config. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251216123421.124401-1-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-12-15irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driverCosmin Tanislav
The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have an Interrupt Controller (ICU) that supports interrupts from external pins IRQ0 to IRQ15, and SEI, and software-triggered interrupts INTCPU0 to INTCPU15. INTCPU0 to INTCPU13, IRQ0 to IRQ13 are non-safety interrupts, while INTCPU14, INTCPU15, IRQ14, IRQ15 and SEI are safety interrupts, and are exposed via a separate register space. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20251201112933.488801-3-cosmin-gabriel.tanislav.xa@renesas.com
2025-12-06Merge tag 'bitmap-for-6.19' of github.com:/norov/linuxLinus Torvalds
Pull bitmap updates from Yury Norov: - Runtime field_{get,prep}() (Geert) - Rust ID pool updates (Alice) - min_t() simplification (David) - __sw_hweightN kernel-doc fixes (Andy) - cpumask.h headers cleanup (Andy) * tag 'bitmap-for-6.19' of github.com:/norov/linux: (32 commits) rust_binder: use bitmap for allocation of handles rust: id_pool: do not immediately acquire new ids rust: id_pool: do not supply starting capacity rust: id_pool: rename IdPool::new() to with_capacity() rust: bitmap: add BitmapVec::new_inline() rust: bitmap: add MAX_LEN and MAX_INLINE_LEN constants cpumask: Don't use "proxy" headers soc: renesas: Use bitfield helpers clk: renesas: Use bitfield helpers ALSA: usb-audio: Convert to common field_{get,prep}() helpers soc: renesas: rz-sysc: Convert to common field_get() helper pinctrl: ma35: Convert to common field_{get,prep}() helpers iio: mlx90614: Convert to common field_{get,prep}() helpers iio: dac: Convert to common field_prep() helper gpio: aspeed: Convert to common field_{get,prep}() helpers EDAC/ie31200: Convert to common field_get() helper crypto: qat - convert to common field_get() helper clk: at91: Convert to common field_{get,prep}() helpers bitfield: Add non-constant field_{prep,get}() helpers bitfield: Add less-checking __FIELD_{GET,PREP}() ...
2025-11-24soc: renesas: Use bitfield helpersGeert Uytterhoeven
Use the field_get() helper, instead of open-coding the same operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
2025-11-24soc: renesas: rz-sysc: Convert to common field_get() helperGeert Uytterhoeven
Drop the driver-specific field_get() macro, in favor of the globally available variant from <linux/bitfield.h>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
2025-11-24soc: renesas: rz-sysc: #undef field_get() before local definitionGeert Uytterhoeven
Prepare for the advent of a globally available common field_get() macro by undefining the symbol before defining a local variant. This prevents redefinition warnings from the C preprocessor when introducing the common macro later. Suggested-by: Yury Norov <yury.norov@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
2025-11-13soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap configClaudiu Beznea
Not all system controller registers are accessible from Linux. Accessing such registers generates synchronous external abort. Populate the readable_reg and writeable_reg members of the regmap config to inform the regmap core which registers can be accessed. The list will need to be updated whenever new system controller functionality is exported through regmap. Fixes: 2da2740fb9c8 ("soc: renesas: rz-sysc: Add syscon/regmap support") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251105070526.264445-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-11-13soc: renesas: r9a09g056-sys: Populate max_registerClaudiu Beznea
Populate max_register to avoid external aborts. Fixes: 2da2740fb9c8 ("soc: renesas: rz-sysc: Add syscon/regmap support") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251105070526.264445-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-23soc: renesas: rcar-rst: Keep RESBAR2S in default stateWolfram Sang
Unlike Gen2, Gen4 has bit 15 of WDTRSTCR register also used. Keep it in the default state for the V3U firmware workaround. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251017114234.2968-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-09-11soc: renesas: Identify R-Car X5HDuy Nguyen
Add support for identifying the R-Car X5H SoC. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Huy Bui <huy.bui.wm@renesas.com> [Kuninori: tidyup for upstreaming] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/87ldmnvzei.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-20soc: renesas: rz-sysc: Add syscon/regmap supportJohn Madieu
The RZ/G3E system controller has various registers that control or report some properties specific to individual IPs. The regmap is registered as a syscon device to allow these IP drivers to access the registers through the regmap API. As other RZ SoCs might have custom read/write callbacks or max-offsets, register a custom regmap configuration. [claudiu.beznea: - do not check the match->data validity in rz_sysc_probe() as it is always valid - dinamically allocate regmap_cfg] Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250818162859.9661-2-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-07treewide: rename GPIO set callbacks back to their original namesBartosz Golaszewski
The conversion of all GPIO drivers to using the .set_rv() and .set_multiple_rv() callbacks from struct gpio_chip (which - unlike their predecessors - return an integer and allow the controller drivers to indicate failures to users) is now complete and the legacy ones have been removed. Rename the new callbacks back to their original names in one sweeping change. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-07-08soc: renesas: Sort Renesas Kconfig configsKuninori Morimoto
Renesas Kconfig is using "SoC serial number" for CONFIG symbol, but is using "SoC chip name" for menu description. Because of it, it looks random order when we run "make menuconfig". commit 6d5aded8d57fc ("soc: renesas: Sort driver description title") sorted Renesas Kconfig by menu description title order, but it makes confusable to add new config. Let's unify "ARMxx Platform support for ${CHIP_NUMBER} (${CHIP_NAME}), and sort it again. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/877c0xhk3z.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-13soc: renesas: pwc-rzv2m: Use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250610-gpiochip-set-rv-soc-v1-2-1a0c36c9deed@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-13soc: renesas: Add RZ/N2H (R9A09G087) config optionLad Prabhakar
Add a new Kconfig option, ARCH_R9A09G087, to enable ARM64 platform support for the Renesas RZ/N2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250609203656.333138-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10soc: renesas: Add RZ/T2H (R9A09G077) config optionThierry Bultel
Add a configuration option for the RZ/T2H SoC. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Link: https://lore.kernel.org/20250515141828.43444-4-thierry.bultel.yh@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-05soc: renesas: rz-sysc: Add SoC identification for RZ/V2N SoCLad Prabhakar
Add SoC identification for the RZ/V2N SoC using the System Controller (SYS) block. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250415085438.83856-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14soc: renesas: Add config option for RZ/V2N (R9A09G056) SoCLad Prabhakar
Add a new Kconfig option, ARCH_R9A09G056, to enable ARM64 platform support for the Renesas RZ/V2N SoC. Default this option to "y" when ARCH_RENESAS is enabled, ensuring that support for the RZ/V2N SoC is automatically included. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-09soc: renesas: Kconfig: Enable SoCs by default when ARCH_RENESAS is setLad Prabhakar
Enable various Renesas SoCs by default when ARCH_RENESAS is selected. Adding default y if ARCH_RENESAS to the relevant configurations removes the need to manually enable individual SoCs in defconfig files. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250401090133.68146-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-20soc: renesas: r9a09g057-sys: Add a callback to print SoC-specific extra featuresJohn Madieu
Some RZ/V2H SoC variants feature a Mali-G31 (GPU) and/or a Mali-C55 (ISP) IP(s). Detect and inform about their presence during SoC identification. Also detect PLL frequency and warn in case of mismatch. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Link: https://lore.kernel.org/20250128031342.52675-6-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-20soc: renesas: rz-sysc: Move RZ/V2H SoC detection to the SYS driverJohn Madieu
As per the other SoC variant of the same family, the system controller provides SoC ID in its own registers. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250128031342.52675-5-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-20soc: renesas: rz-sysc: Add support for RZ/G3E familyJohn Madieu
Add SoC detection support for the RZ/G3E SoC. Also add support for detecting the number of cores and the ETHOS-U55 NPU, and also detect PLL mismatch for SW settings other than 1.7GHz. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250128031342.52675-4-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-20soc: renesas: rz-sysc: Move RZ/G3S SoC detection to the SYSC driverClaudiu Beznea
Now that we have SoC detection in the RZ SYSC driver, move the RZ/G3S SoC detection to it. The SYSC provides SoC ID in its own registers. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Link: https://lore.kernel.org/20250128031342.52675-3-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-20soc: renesas: Add SYSC driver for Renesas RZ familyClaudiu Beznea
The RZ/G3S system controller (SYSC) has various registers that control different functionalities. One of the exposed register offers information about the SoC identification. Add a driver that identifies the SoC. Later the driver will be extended with other functionalities. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250128031342.52675-2-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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