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path: root/drivers/gpu
AgeCommit message (Expand)Author
2025-11-19drm/panel: sofef00: Introduce compatible which includes the panel nameDavid Heidelberg
2025-11-19drm/panel: sofef00: Initialise at 50% brightnessCasey Connolly
2025-11-19drm/panel: sofef00: Add prepare_prev_first flag to drm_panelCasey Connolly
2025-11-19drm/panel: sofef00: Introduce page macroDavid Heidelberg
2025-11-19drm/panel: sofef00: Split sending commands to the enable/disable functionsDavid Heidelberg
2025-11-19drm/panel: sofef00: Handle all regulatorsDavid Heidelberg
2025-11-19drm/panel: sofef00: Clean up panel description after s6e3fc2x01 removalDavid Heidelberg
2025-11-19drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panelChaoyi Chen
2025-11-19drm/panel: ronbo-rb070d30: fix warning with gpio controllers that sleepJosua Mayer
2025-11-19drm/panel: jadard-jd9365da-h3: Use dev_err_probe() instead of DRM_DEV_ERROR()...Abhishek Rajput
2025-11-19drm/panel: simple: Add Raystar RFF500F-AWH-DNN panel entryFabio Estevam
2025-11-19gpu/drm: panel: simple-panel: add Samsung LTL106AL01 LVDS panel supportSvyatoslav Ryhel
2025-11-19gpu/drm: panel: add support for LG LD070WX3-SL01 MIPI DSI panelSvyatoslav Ryhel
2025-11-19drm/xe/vm: Use for_each_tlb_inval() to calculate invalidation fencesMatt Roper
2025-11-19Merge drm/drm-fixes into drm-misc-fixesThomas Zimmermann
2025-11-19drm/i915/cx0: Enable dpll framework for MTL+Mika Kahola
2025-11-19drm/i915/cx0: Add MTL+ Thunderbolt PLL hooksImre Deak
2025-11-19drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLsMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDIMika Kahola
2025-11-19drm/i915/cx0: PLL verify debug state printImre Deak
2025-11-19drm/i915/cx0: Add MTL+ .crtc_get_dpll hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_freq hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Add .compare_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .dump_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .update_active_dpll hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .put_dplls hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_dplls hookMika Kahola
2025-11-19drm/i915/cx0: Compute plls for MTL+ platformMika Kahola
2025-11-19drm/xe: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/vblank: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/i915/cx0: Update C10/C20 state calculationMika Kahola
2025-11-19drm/i915/cx0: Add PLL information for MTL+Mika Kahola
2025-11-19drm/i915/cx0: Remove state verificationMika Kahola
2025-11-19drm/i915/cx0: Print additional Cx0 PLL HW stateImre Deak
2025-11-19drm/i915/cx0: Zero Cx0 PLL state before compute and HW readoutImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL port clock from PLL stateImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL DP mode from PLL stateImre Deak
2025-11-19drm/i915/cx0: Read out the Cx0 PHY SSC enabled stateImre Deak
2025-11-19drm/i915/cx0: Sanitize C10 PHY PLL SSC register setupImre Deak
2025-11-19drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Add macro to get DDI port width from a register valueImre Deak
2025-11-19drm/i915/cx0: Move definition of Cx0 PHY functions earlierImre Deak
2025-11-19drm/i915/cx0: Track the C20 PHY VDR state in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Sanitize calculating C20 PLL state from tablesImre Deak
2025-11-19drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flagImre Deak
2025-11-19drm/i915/cx0: Factor out C10 msgbus access start/end helpersImre Deak
2025-11-19drm/i915/cx0: Rename TBT functions to be ICL specificMika Kahola
2025-11-19drm/msm: Switch to use %ptSpAndy Shevchenko
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