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path: root/drivers/gpu
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2024-05-06drm/i915: pass dev_priv explicitly to PORT_ALPM_CTLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PORT_ALPM_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/86e8f5649c822ff6fa0502ad88964bfcb269c6c5.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06FIXME drm/i915: pass dev_priv explicitly to ALPM_CTL2Jani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ALPM_CTL2 register macro. Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/09acf2751cfd2f524e6ba97c3ac285495eae5c86.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to ALPM_CTLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ALPM_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/96da9be36dc93fa9a7c329f25ff963e4998998c1.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPTJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_SRCSZ_ERLY_TPT register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b37217f55702fc10190c2c5aded7d845a36766f6.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR2_MAN_TRK_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/72934c8ac3a923ca0c12fc6cdeec1e0b87ecc4a4.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to PSR2_SU_STATUSJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR2_SU_STATUS register macro. v2: Expand from _PSR2_SU_STATUS to PSR2_SU_STATUS (Rodrigo) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240502103925.1829104-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUSJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR2_STATUS register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/5d86a48f51ae6fa4c5a3abf098440a94d07de870.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to PSR_EVENTJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR_EVENT register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9bc5819afa46416eb8f12ac050ed4d3bcde34b63.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR2_CTLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR2_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e7df99445716ce404bbfe733dd962288a529cf0d.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUGJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_DEBUG register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/187dd49632d46e67705bd258ed7f9eabdeb108b2.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNTJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_PERF_CNT register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/21805960967ab88c1418037b98fe3e051eb00608.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_STATUSJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_STATUS register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4aaa0187b16d2b96b5b4b1d775d7349c9fc28c7c.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATAJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_AUX_DATA register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4e3dc15b170c2b64168e46ebf1802d63df34b4a2.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_AUX_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/66ec1f81be49c87cd9613ba052ce6fd50362d0e0.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IIRJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_PSR_IIR register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/3a03109d11e7f55a456c3e5ef28d3ffa69582d3d.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IMRJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_PSR_IMR register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/09e9c11ffb669dac901c2416462a8f3dabc86020.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_CTLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/198858bc3925c02c0975670e3ebb5ce2084ac658.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_EXITLINEJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_EXITLINE register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/eb1e5fe155daf2d271af76e683a1f3f33e34403a.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-05drm/msm: Add devcoredump support for a750Connor Abbott
Add an a750 case to the various places where we choose a list of registers. Patchwork: https://patchwork.freedesktop.org/patch/592519/ Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/592519 Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-05drm/msm: Adjust a7xx GBIF debugbus dumpingConnor Abbott
Use the kgsl-style list of indices, because this is about to change for a750 and we want to reuse the downstream header directly. Patchwork: https://patchwork.freedesktop.org/patch/592520/ Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/592520 Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-04drm/msm: Update a6xx registers XMLConnor Abbott
Update to Mesa commit e82d70d472cc ("freedreno/a7xx: Add A7XX_HLSQ_DP_STR location from kgsl"). Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/592518/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-04drm/msm: Fix imported a750 snapshot header for upstreamConnor Abbott
Add A7XX prefixes necessary because we use the same code for dumping a6xx and a7xx, fix register name prefixes for upstream, and use the upstream header. Patchwork: https://patchwork.freedesktop.org/patch/592517/ Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/592517 Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-04drm/msm: Import a750 snapshot registers from kgslConnor Abbott
Import from kgsl commit 809ee24fe560. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/592516/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-04drm/msm/a6xx: Avoid a nullptr dereference when speedbin setting failsKonrad Dybcio
Calling a6xx_destroy() before adreno_gpu_init() leads to a null pointer dereference on: msm_gpu_cleanup() : platform_set_drvdata(gpu->pdev, NULL); as gpu->pdev is only assigned in: a6xx_gpu_init() |_ adreno_gpu_init |_ msm_gpu_init() Instead of relying on handwavy null checks down the cleanup chain, explicitly de-allocate the LLC data and free a6xx_gpu instead. Fixes: 76efc2453d0e ("drm/msm/gpu: Fix crash during system suspend after unbind") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/588919/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-04drm/msm/adreno: fix CP cycles stat retrieval on a7xxZan Dobersek
a7xx_submit() should use the a7xx variant of the RBBM_PERFCTR_CP register for retrieving the CP cycles value before and after the submitted command stream execution. Signed-off-by: Zan Dobersek <zdobersek@igalia.com> Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") Patchwork: https://patchwork.freedesktop.org/patch/588445/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-04drm/msm/a7xx: allow writing to CP_BV counter selection registersZan Dobersek
In addition to the CP_PERFCTR_CP_SEL register range, allow writes to the CP_BV_PERFCTR_CP_SEL registers in the 0x8e0-0x8e6 range for profiling purposes of tools like fdperf and perfetto. Signed-off-by: Zan Dobersek <zdobersek@igalia.com> Patchwork: https://patchwork.freedesktop.org/patch/580548/ [fixup a730_protect size] Signed-off-by: Rob Clark <robdclark@chromium.org>
2024-05-03drm/xe: Demote CCS_MODE info to debug onlyRodrigo Vivi
This information is printed in any gt_reset, which actually occurs in any runtime resume, what can be so verbose in production build. Let's demote it to debug only. Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240503190331.6690-1-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-05-03drm/xe/bmg: Enable the display supportBalasubramani Vivekanandan
Enable the display support for Battlemage Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-20-radhakrishna.sripada@intel.com
2024-05-03drm/i915/display: perform transient flushMatthew Auld
Perform manual transient cache flush prior to flip and at the end of frontbuffer_flush. This is needed to ensure display engine doesn't see garbage if the surface is L3:XD dirty. Testcase: igt@xe-pat@display-vs-wb-transient Signed-off-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Acked-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-19-radhakrishna.sripada@intel.com
2024-05-03drm/xe/device: implement transient flushNirmoy Das
Display surfaces can be tagged as transient by mapping it using one of the various L3:XD PAT index modes on Xe2. The expectation is that KMD needs to request transient data flush at the start of flip sequence to ensure all transient data in L3 cache is flushed to memory. Add a routine for this which we can then call from the display code. v2: rebase(RK) Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Co-developed-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-18-radhakrishna.sripada@intel.com
2024-05-03drm/xe/gt_print: add xe_gt_err_once()Matthew Auld
Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-17-radhakrishna.sripada@intel.com
2024-05-03drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5Balasubramani Vivekanandan
Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate to it. Bspec: 67066 Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-16-radhakrishna.sripada@intel.com
2024-05-03Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"Ankit Nautiyal
This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f. For BMG it seems that the VBT to DDI mapping does not follow DG1, and DG2, but follows ADLP mapping given in Bspec:20124. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-15-radhakrishna.sripada@intel.com
2024-05-03drm/i915/bmg: BMG should re-use MTL's south display logicMatt Roper
Battlemage's south display is the same as Meteor Lake's, including the need to invert the HPD pins, which Lunar Lake does not need. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-14-radhakrishna.sripada@intel.com
2024-05-03drm/i915/xe2hpd: Do not program MBUS_DBOX BW creditsJosé Roberto de Souza
No display IP beyond Xe_LPD+ has "BW credits" bits in MBUS_DBOX_CTL register. Restrict the programming only to Xe_LPD+. BSpec: 49213 CC: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-13-radhakrishna.sripada@intel.com
2024-05-03drm/i915/xe2hpd: Add max memory bandwidth algorithmMatt Roper
Unlike DG2, Xe2_HPD does support multiple GV points with different maximum memory bandwidths, but uses a much simpler algorithm than igpu platforms use. Bspec: 64631 CC: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-12-radhakrishna.sripada@intel.com
2024-05-03drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planesAnusha Srivatsa
Add step 9 from initialize display sequence. v2: Commit subject improved Bpsec: 49189 Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-11-radhakrishna.sripada@intel.com
2024-05-03drm/i915/xe2hpd: Add display infoLucas De Marchi
Add initial display info for xe2hpd. It is similar to xelpdp, but with no PORT_B. v2: Inherit from XE_LPDP_FEATURES instead of XE_LPD_FEATURES Bspec: 67066 CC: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-10-radhakrishna.sripada@intel.com
2024-05-03drm/i915/xe2hpd: update pll values in sync with BspecRavi Kumar Vodapalli
DP/eDP and HDMI pll values are updated for Xe2_HPD platform v2: Removed the unsupported mtl_c20_dp_uhbr20 from xehpd_c20_dp_tables Bspec: 74165 Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-9-radhakrishna.sripada@intel.com
2024-05-03drm/i915/xe2hpd: Add support for eDP PLL configurationBalasubramani Vivekanandan
Tables for eDP PHY PLL configuration for different link rates added for Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas Xe2_HPD has C20 PHY. v2: Updated with a more appropriate Bspec number. Bspec: 74165 CC: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-8-radhakrishna.sripada@intel.com
2024-05-03drm/i915/xe2hpd: Add new C20 PHY SRAM addressBalasubramani Vivekanandan
Xe2_HPD has different offsets for C20 PHY SRAM configuration context location. Use the display version to select the right address. Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e. MTL's display). According to the BSpec, currently, only Xe2_HPD has different offsets, so make sure it is the only display using them in the driver. v2: * Redesigned how the right offsets are selected for different display IP versions. v3: Fix white space error(RK) Bspec: 67610 Cc: Clint Taylor <Clinton.A.Taylor@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-7-radhakrishna.sripada@intel.com
2024-05-03drm/i915/xe2hpd: Properly disable power in port AJosé Roberto de Souza
Xe2_HPD has a different value to power down port A. BSpec: 65450 Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-6-radhakrishna.sripada@intel.com
2024-05-03drm/i915/bmg: Extend DG2 tc check to futureRadhakrishna Sripada
Discrete cards use the Port numbers TC1-4 for the offsets. The regular flow for type-c subsystem port initialization can be skipped. This check is present in DG2. Extend this to future discrete products. Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-5-radhakrishna.sripada@intel.com
2024-05-03drm/i915/xe2hpd: Initial cdclk tableClint Taylor
Add Xe2_HPD specific CDCLK table and use MTL Funcs. Bspec: 65243 CC: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-4-radhakrishna.sripada@intel.com
2024-05-03drm/i915/bmg: Define IS_BATTLEMAGE macroBalasubramani Vivekanandan
Display code uses IS_BATTLEMAGE macro but the platform support doesn't exist in i915. So fake IS_BATTLEMAGE macro defined to enable building i915 code. We should make sure the macro parameter is used in the always-false expression so that we don't run into "unused variable" warnings from i915 builds if the IS_BATTLEMAGE() check is the only place the i915 pointer gets used in a function. While we're at it, also update the IS_LUNARLAKE macro to include the parameter in the false expression for consistency. Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-3-radhakrishna.sripada@intel.com
2024-05-03drm/i915/bmg: Lane reversal requires writes to both context lanesClint Taylor
Write both CX0 Lanes for Context Toggle for all except TC pin assignment D. v2: Update title(RK) Bspec: 64539 CC: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-2-radhakrishna.sripada@intel.com
2024-05-03Merge drm/drm-next into drm-intel-nextRodrigo Vivi
A backmerge to sync xe and i915 and allow us to merge "Enable display support for Battlemage" series through drm-intel Link: https://patchwork.freedesktop.org/series/132429/ Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-05-03drm/amdgpu: remove ip dump reg_count variableSunil Khatri
reg_count is not used and the register count is directly derived from the array size and hence removed. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-03drm/amd/display: Fix uninitialized variables in dcn401 and dml21Alex Hung
This fixes 12 UNINIT issues reported by Coverity. Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-03drm/amd/display: Assign disp_cfg_index_max when dml21Alex Hung
[WHY & HOW] The assignment of disp_cfg_index_max is missed and should be assigned to __DML2_WRAPPER_MAX_STREAMS_PLANES__. Fixes: 55ec7679e6a5 ("drm/amd/display: Limit array index according to architecture") Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-28 17:35:52 +0000