summaryrefslogtreecommitdiff
path: root/drivers/gpu
AgeCommit message (Expand)Author
2024-05-06drm/i915: pass dev_priv explicitly to PORT_ALPM_CTLJani Nikula
2024-05-06FIXME drm/i915: pass dev_priv explicitly to ALPM_CTL2Jani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to ALPM_CTLJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPTJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTLJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to PSR2_SU_STATUSJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUSJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to PSR_EVENTJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR2_CTLJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUGJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNTJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_STATUSJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATAJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTLJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IIRJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IMRJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_CTLJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_EXITLINEJani Nikula
2024-05-05drm/msm: Add devcoredump support for a750Connor Abbott
2024-05-05drm/msm: Adjust a7xx GBIF debugbus dumpingConnor Abbott
2024-05-04drm/msm: Update a6xx registers XMLConnor Abbott
2024-05-04drm/msm: Fix imported a750 snapshot header for upstreamConnor Abbott
2024-05-04drm/msm: Import a750 snapshot registers from kgslConnor Abbott
2024-05-04drm/msm/a6xx: Avoid a nullptr dereference when speedbin setting failsKonrad Dybcio
2024-05-04drm/msm/adreno: fix CP cycles stat retrieval on a7xxZan Dobersek
2024-05-04drm/msm/a7xx: allow writing to CP_BV counter selection registersZan Dobersek
2024-05-03drm/xe: Demote CCS_MODE info to debug onlyRodrigo Vivi
2024-05-03drm/xe/bmg: Enable the display supportBalasubramani Vivekanandan
2024-05-03drm/i915/display: perform transient flushMatthew Auld
2024-05-03drm/xe/device: implement transient flushNirmoy Das
2024-05-03drm/xe/gt_print: add xe_gt_err_once()Matthew Auld
2024-05-03drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5Balasubramani Vivekanandan
2024-05-03Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"Ankit Nautiyal
2024-05-03drm/i915/bmg: BMG should re-use MTL's south display logicMatt Roper
2024-05-03drm/i915/xe2hpd: Do not program MBUS_DBOX BW creditsJosé Roberto de Souza
2024-05-03drm/i915/xe2hpd: Add max memory bandwidth algorithmMatt Roper
2024-05-03drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planesAnusha Srivatsa
2024-05-03drm/i915/xe2hpd: Add display infoLucas De Marchi
2024-05-03drm/i915/xe2hpd: update pll values in sync with BspecRavi Kumar Vodapalli
2024-05-03drm/i915/xe2hpd: Add support for eDP PLL configurationBalasubramani Vivekanandan
2024-05-03drm/i915/xe2hpd: Add new C20 PHY SRAM addressBalasubramani Vivekanandan
2024-05-03drm/i915/xe2hpd: Properly disable power in port AJosé Roberto de Souza
2024-05-03drm/i915/bmg: Extend DG2 tc check to futureRadhakrishna Sripada
2024-05-03drm/i915/xe2hpd: Initial cdclk tableClint Taylor
2024-05-03drm/i915/bmg: Define IS_BATTLEMAGE macroBalasubramani Vivekanandan
2024-05-03drm/i915/bmg: Lane reversal requires writes to both context lanesClint Taylor
2024-05-03Merge drm/drm-next into drm-intel-nextRodrigo Vivi
2024-05-03drm/amdgpu: remove ip dump reg_count variableSunil Khatri
2024-05-03drm/amd/display: Fix uninitialized variables in dcn401 and dml21Alex Hung
2024-05-03drm/amd/display: Assign disp_cfg_index_max when dml21Alex Hung
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-28 20:39:42 +0000