summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915
AgeCommit message (Expand)Author
2025-11-19drm/i915/rps: postpone i915 fence check to boostJani Nikula
2025-11-19drm/i915/rps: call RPS functions via the parent interfaceJani Nikula
2025-11-19drm/i915/rps: store struct dma_fence in struct wait_rps_boostJani Nikula
2025-11-19drm/i915: add .has_fenced_regions to parent interfaceJani Nikula
2025-11-19drm/i915: add .vgpu_active to parent interfaceJani Nikula
2025-11-19drm/{i915,xe}/display: move irq calls to parent interfaceJani Nikula
2025-11-19drm/i915/display: convert the display irq interfaces to struct intel_displayJani Nikula
2025-11-19drm/{i915, xe}/display: duplicate gen2 irq/error init/reset in display irqJani Nikula
2025-11-19drm/i915/dram: Fix ICL DIMM_S decodingVille Syrjälä
2025-11-19drm/i915/dram: Sort SKL+ DIMM register bitsVille Syrjälä
2025-11-19drm/i915/dram: Use REG_GENMASK() & co. for the SKL+ DIMM regsVille Syrjälä
2025-11-19drm/i915/cx0: Enable dpll framework for MTL+Mika Kahola
2025-11-19drm/i915/cx0: Add MTL+ Thunderbolt PLL hooksImre Deak
2025-11-19drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLsMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDIMika Kahola
2025-11-19drm/i915/cx0: PLL verify debug state printImre Deak
2025-11-19drm/i915/cx0: Add MTL+ .crtc_get_dpll hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_freq hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Add .compare_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .dump_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .update_active_dpll hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .put_dplls hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_dplls hookMika Kahola
2025-11-19drm/i915/cx0: Compute plls for MTL+ platformMika Kahola
2025-11-19drm/i915/cx0: Update C10/C20 state calculationMika Kahola
2025-11-19drm/i915/cx0: Add PLL information for MTL+Mika Kahola
2025-11-19drm/i915/cx0: Remove state verificationMika Kahola
2025-11-19drm/i915/cx0: Print additional Cx0 PLL HW stateImre Deak
2025-11-19drm/i915/cx0: Zero Cx0 PLL state before compute and HW readoutImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL port clock from PLL stateImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL DP mode from PLL stateImre Deak
2025-11-19drm/i915/cx0: Read out the Cx0 PHY SSC enabled stateImre Deak
2025-11-19drm/i915/cx0: Sanitize C10 PHY PLL SSC register setupImre Deak
2025-11-19drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Add macro to get DDI port width from a register valueImre Deak
2025-11-19drm/i915/cx0: Move definition of Cx0 PHY functions earlierImre Deak
2025-11-19drm/i915/cx0: Track the C20 PHY VDR state in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Sanitize calculating C20 PLL state from tablesImre Deak
2025-11-19drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flagImre Deak
2025-11-19drm/i915/cx0: Factor out C10 msgbus access start/end helpersImre Deak
2025-11-19drm/i915/cx0: Rename TBT functions to be ICL specificMika Kahola
2025-11-19drm/i915/fbdev: Hold runtime PM ref during fbdev BO creationDibin Moolakadan Subrahmanian
2025-11-18drm/i915/xe3: Restrict PTL intel_encoder_is_c10phy() to only PHY ADnyaneshwar Bhadane
2025-11-18drm/i915/display: Add definition for wcl as subplatformDnyaneshwar Bhadane
2025-11-18drm/pcids: Split PTL pciids group to make wcl subplatformDnyaneshwar Bhadane
2025-11-18drm/i915/fbc: Apply Wa_15018326506Vinod Govindapillai
2025-11-17drm/i915/xe3lpd: Load DMC for Xe3_LPD version 30.02Dnyaneshwar Bhadane
2025-11-18Merge tag 'drm-intel-gt-next-2025-11-14' of https://gitlab.freedesktop.org/dr...Dave Airlie
generated by cgit v1.2.3 (git 2.25.1) at 2026-07-12 16:01:43 +0000