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path: root/drivers/gpu/drm/i915
AgeCommit message (Expand)Author
2025-08-19drm/i915/dram: bypass fsb/mem freq detection on dg2 and no displayJani Nikula
2025-08-19drm/i915/rps: use intel_fsb_freq() and intel_mem_freq()Jani Nikula
2025-08-19drm/i915/dram: add intel_mem_freq()Jani Nikula
2025-08-19drm/i915/dram: add intel_fsb_freq() and use itJani Nikula
2025-08-19drm/i915/switcheroo: check for NULL before dereferencingJani Nikula
2025-08-19drm/i915/gt: Relocate compression repacking WA for JSL/EHLSebastian Brzezinka
2025-08-19drm/i915: silence rpm wakeref asserts on GEN11_GU_MISC_IIR accessJani Nikula
2025-08-19drm/i915/dp: Set min_bpp limit to 30 in HDR modeChaitanya Kumar Borah
2025-08-19drm/i915/dp: Refactor intel_dp_in_hdr_mode() for broader reuseChaitanya Kumar Borah
2025-08-18drm/i915/gt: Relocate Gen6 context-specific workaroundSebastian Brzezinka
2025-08-18drm/i915/gt: Relocate Gen7 context-specific workaroundsSebastian Brzezinka
2025-08-18drm/i915/gt: Relocate compression repacking WA for JSL/EHLSebastian Brzezinka
2025-08-18drm/i915/icl+/tc: Convert AUX powered WARN to a debug messageImre Deak
2025-08-18drm/i915/lnl+/tc: Use the cached max lane count valueImre Deak
2025-08-18drm/i915/lnl+/tc: Fix max lane count HW readoutImre Deak
2025-08-18drm/i915/icl+/tc: Cache the max lane count valueImre Deak
2025-08-18drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sinkImre Deak
2025-08-15drm/i915/bo: remove unnecessary includeJani Nikula
2025-08-15drm/i915/audio: drop irq enabled check from LPE audio setupJani Nikula
2025-08-15drm/i915/active: Use try_cmpxchg64() in __active_lookup()Uros Bizjak
2025-08-14drm/i915/display: drop __to_intel_display() usageJani Nikula
2025-08-14drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_DJani Nikula
2025-08-14drm/i915/gvt: convert mmio table to struct intel_displayJani Nikula
2025-08-14drm/i915/uncore: pass display to HAS_FPGA_DBG_UNCLAIMED()Jani Nikula
2025-08-14drm/i915/drv: pass display to HAS_DISPLAY()Jani Nikula
2025-08-14drm/i915/switcheroo: pass display to HAS_DISPLAY()Jani Nikula
2025-08-14drm/i915/gem: pass display to HAS_DISPLAY()Jani Nikula
2025-08-14drm/i915/gmch: pass display to DISPLAY_VER()Jani Nikula
2025-08-14drm/i915/dram: pass display to macros that expect displayJani Nikula
2025-08-14drm/i915/irq: pass display to macros that expect displayJani Nikula
2025-08-14drm/i915/clockgating: pass display to DSPCNTR and DSPSURF register macrosJani Nikula
2025-08-14drm/i915/clockgating: pass display to HAS_PCH_*() macrosJani Nikula
2025-08-14drm/i915/clockgating: pass display to for_each_pipe()Jani Nikula
2025-08-14drm/i915/fb: pass display to HAS_GMCH() and DISPLAY_VER()Jani Nikula
2025-08-14drm/i915/display: pass display to HAS_PCH_*() macrosJani Nikula
2025-08-14drm/i915: silence rpm wakeref asserts on GEN11_GU_MISC_IIR accessJani Nikula
2025-08-13drm/i915/wcl: Add display device infoImre Deak
2025-08-13drm/i915/display: Add power well mapping for WCLChaitanya Kumar Borah
2025-08-13drm/i915/tc: Debug print the pin assignment and max lane countImre Deak
2025-08-13drm/i915/tc: Cache the pin assignment valueImre Deak
2025-08-13dmc/i915/tc: Report pin assignment NONE in TBT-alt modeImre Deak
2025-08-13drm/i915/tc: Pass intel_tc_port to internal lane mask/count helpersImre Deak
2025-08-13drm/i915/tc: Handle non-TC encoders when getting the pin assignmentImre Deak
2025-08-13drm/i915/tc: Unify the way to get the max lane count value on MTL+Imre Deak
2025-08-13drm/i915/tc: Unify the way to get the pin assignment on all platformsImre Deak
2025-08-13drm/i915/tc: Validate the pin assignment on all platformsImre Deak
2025-08-13drm/i915/tc: Handle pin assignment NONE on all platformsImre Deak
2025-08-13drm/i915/tc: Pass pin assignment value around using the pin assignment enumImre Deak
2025-08-13drm/i915/tc: Add an enum for the TypeC pin assignmentImre Deak
2025-08-13drm/i915/tc: Move asserting the power state after reading TCSS_DDI_STATUSImre Deak
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