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path: root/drivers/gpu/drm/i915/Makefile
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2026-05-05drm/i915: move SKL clock gating init to displayLuca Coelho
Move the SKL-specific display clock gating programming into a new file inside display. This removes dependency from intel_clock_gating.c to the display's intel_pch.h file, so we can remove the include statement. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260428095104.818360-2-luciano.coelho@intel.com Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2026-04-07drm/i915: move intel_fb_pin.c to i915_fb_pin.cJani Nikula
intel_fb_pin.c is the final file in display/ that's specific to i915 only. Move it to i915 core, renaming it to i915_fb_pin.c. It'll still depend on a lot of display stuff, unfortunately. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/ab1ffc08bcd1364715396142f91780b6261bbe65.1775556190.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-04-02drm/{i915, xe}: move fbdev fb calls to parent interfaceJani Nikula
Move the driver specific fbdev fb calls to the display parent interface. Reuse the existing struct intel_display_bo_interface, as this is mostly about gem objects. Put everything behind IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION) to catch configuration issues at build or link time. v2: Rebase Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> # v1 Link: https://patch.msgid.link/a6bb24909a58181cfc41b91a4c6538a181d27158.1774950508.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-04-01drm/i915/mchbar: Provide intel_mchbar_read*() abstractionVille Syrjälä
MCHBAR registers are a bit special in that: - we access them through the mirror - the mirror is read only on HSW+ - the mirror requires the actual MCHBAR to be enabled in device 0:0.0 - the mirror is gone on MTL+ So I'd prefer to treat MCHBAR registers as a bit special in the code as well, and do all accesses to them via dedicated functions. Prodive such functions in the form of intel_mchbar_read*(). v2: Put the function arguments on one line No intel_uncore_read64() on xe, use intel_uncore_read64_2x32() Name the new function intel_mchbar_read64_2x32() as well Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260331154259.24600-3-ville.syrjala@linux.intel.com
2026-03-24drm/i915/de: Introduce intel_de.c and move intel_de_{read,write}8() thereVille Syrjälä
intel_de_{read,write}8() aren't performance critical so having them as static inline is pointless. Introduce intel_de.c and move the implementation there. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260313111028.25159-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2026-03-16drm/{i915,xe}: move framebuffer bo to parent interfaceJani Nikula
Add .framebuffer_init, .framebuffer_fini and .framebuffer_lookup to the bo parent interface. While they're about framebuffers, they're specifically about framebuffer objects, so the bo interface is a good enough fit, and there's no need to add another interface struct. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/848d32a44bf844cba3d66e44ba9f20bea4a8352d.1773238670.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-03-16drm/{i915, xe}/bo: move display bo calls to parent interfaceJani Nikula
Continue i915 and xe separation from display by moving the bo calls to the display parent interface. Instead of adding all these functions to intel_parent.[ch], reuse the now vacated intel_bo.[ch], and avoid mass renames to calls of these functions. This is similar to intel_display_rpm.[ch]. Make many of the hooks optional to avoid having to implement dummy functions in xe. Indeed now we can remove many of the existing dummy functions. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/7899eef2ccf0cd603df69099df065226a0df917b.1773238670.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-03-16drm/i915: move i915 specific bo implementation to i915Jani Nikula
The bo interface implementation is different for both i915 and xe. Move the i915 specific implementation from display to i915 core. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/e159166d623899996a51a577365ca7ab9b1a0974.1773238670.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-02-27drm/i915/overlay: Move i915 specific code into i915_overlay.cVille Syrjälä
Relocate the i915 driver specific parts of the overlay code into i915_overlay.c. This leaves intel_overlay.c with just the display specific code. The one annoyance here is the DSPCLK_GATE_D register access being done from i830_overlay_clock_gating(). The register definition lives on the display side as we do need to access it on other platforms there. Since it's just one register and bit, I decided to just duplicate that part in i915_reg.h. v2: Use kzalloc_obj() Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260226133855.17690-1-ville.syrjala@linux.intel.com
2026-02-26drm/i915/dpt: drop _common from the DPT file namesJani Nikula
With the intel_dpt.[ch] file names vacated, and i915 specific code moved away, we can rename the intel_dpt_common.[ch] files to the simpler name. Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Link: https://patch.msgid.link/3f2da737a26bb71a7bc05a3e6c456302e3c72656.1772030909.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-02-26drm/i915/dpt: move display/intel_dpt.c to i915_dpt.cJani Nikula
The DPT implementation is i915 specific. The xe driver has a different implementation. Move display/intel_dpt.c to i915_dpt.c. Cleanups will follow. Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Link: https://patch.msgid.link/20a3bfb2762f39f9666d9a5752b8d2fb133583b0.1772030909.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-02-25Merge drm/drm-next into drm-intel-nextJani Nikula
Sync with v7.0-rc1 which contains a few treewide changes affecting i915. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-02-11Merge tag 'drm-next-2026-02-11' of https://gitlab.freedesktop.org/drm/kernelLinus Torvalds
Pull drm updates from Dave Airlie: "Highlights: - amdgpu support for lots of new IP blocks which means newer GPUs - xe has a lot of SR-IOV and SVM improvements - lots of intel display refactoring across i915/xe - msm has more support for gen8 platforms - Given up on kgdb/kms integration, it's too hard on modern hw core: - drop kgdb support - replace system workqueue with percpu - account for property blobs in memcg - MAINTAINERS updates for xe + buddy rust: - Fix documentation for Registration constructors - Use pin_init::zeroed() for fops initialization - Annotate DRM helpers with __rust_helper - Improve safety documentation for gem::Object::new() - Update AlwaysRefCounted imports - mm: Prevent integer overflow in page_align() atomic: - add drm_device pointer to drm_private_obj - introduce gamma/degamma LUT size check buddy: - fix free_trees memory leak - prevent BUG_ON bridge: - introduce drm_bridge_unplug/enter/exit - add connector argument to .hpd_notify - lots of recounting conversions - convert rockchip inno hdmi to bridge - lontium-lt9611uxc: switch to HDMI audio helpers - dw-hdmi-qp: add support for HPD-less setups - Algoltek AG6311 support panels: - edp: CSW MNE007QB3-1, AUO B140HAN06.4, AUO B140QAX01.H - st75751: add SPI support - Sitronix ST7920, Samsung LTL106HL02 - LG LH546WF1-ED01, HannStar HSD156J - BOE NV130WUM-T08 - Innolux G150XGE-L05 - Anbernic RG-DS dma-buf: - improve sg_table debugging - add tracepoints - call clear_page instead of memset - start to introduce cgroup memory accounting in heaps - remove sysfs stats dma-fence: - add new helpers dp: - mst: avoid oob access with vcpi=0 hdmi: - limit infoframes exposure to userspace gem: - reduce page table overhead with THP - fix leak in drm_gem_get_unmapped_area gpuvm: - API sanitation for rust bindings sched: - introduce new helpers panic: - report invalid panic modes - add kunit tests i915/xe display: - Expose sharpness only if num_scalers is >= 2 - Add initial Xe3P_LPD for NVL - BMG FBC support - Add MTL+ platforms to support dpll framework _ fix DIMM_S DRM decoding on ICL - Return to using AUX interrupts - PSR/Panel replay refactoring - use consolidation HDMI tables - Xe3_LPD CD2X dividier changes xe: - vfio: add vfio_pci for intel GPU - multi queue support - dynamic pagemaps and multi-device SVM - expose temp attribs in hwmon - NO_COMPRESSION bo flag - expose MERT OA unit - sysfs survivability refactor - SRIOV PF: add MERT support - enable SR-IOV VF migration - Enable I2C/NVM on Crescent Island - Xe3p page reclaimation support - introduce SRIOV scheduler groups - add SoC remappt support in system controller - insert compiler barriers in GuC code - define NVL GuC firmware - handle GT resume failure - fix drm scheduler layering violations - enable GSC loading and PXP for PTL - disable GuC Power DCC strategy on PTL - unregister drm device on probe error i915: - move to kernel standard fault injection - bump recommended GuC version for DG2 and MTL amdgpu: - SMUIO 15.x, PSP 15.x support - IH 6.1.1/7.1 support - MMHUB 3.4/4.2 support - GC 11.5.4/12.1 support - SDMA 6.1.4/7.1/7.11.4 support - JPEG 5.3 support - UserQ updates - GC 9 gfx queue reset support - TTM memory ops parallelization - convert legacy logging to new helpers - DC analog fixes amdkfd: - GC 11.5.4/12.1 suppport - SDMA 6.1.4/7.1 support - per context support - increase kfd process hash table - Reserved SDMA rework radeon: - convert legacy logging to new helpers - use devm for i2c adapters msm: - GPU - Document a612/RGMU dt bindings - UBWC 6.0 support (for A840 / Kaanapali) - a225 support - DPU: - Switch to use virtual planes by default - Fix DSI CMD panels on DPU 3.x - Rewrite format handling to remove intermediate representation - Fix watchdog on DPU 8.x+ - Fix TE / Vsync source setting on DPU 8.x+ - Add 3D_Mux on SC7280 - Kaanapali platform support - Fix UBWC register programming - Make RM reserve DSPP-enabled mixers for CRTCs with LMs - Gamma correction support - DP: - Enable support for eDP 1.4+ link rate tables - Fix MDSS1 DP indices on SA8775P, making them to work - Fix msm_dp_ctrl_config_msa() to work with LLVM 20 - DSI: - Document QCS8300 as compatible with SA8775P - Kaanapali platform support - DSI PHY: - switch to divider_determine_rate() - MDP5: - Drop support for MSM8998, SDM660 and SDM630 (switch over to DPU) - MDSS: - Kaanapali platform support - Fixed UBWC register programming nova-core: - Prepare for Turing support. This includes parsing and handling Turing-specific firmware headers and sections as well as a Turing Falcon HAL implementation - Get rid of the Result<impl PinInit<T, E>> anti-pattern - Relocate initializer-specific code into the appropriate initializer - Use CStr::from_bytes_until_nul() to remove custom helpers - Improve handling of unexpected firmware values - Clean up redundant debug prints - Replace c_str!() with native Rust C-string literals - Update nova-core task list nova: - Align GEM object size to system page size tyr: - Use generated uAPI bindings for GpuInfo - Replace manual sleeps with read_poll_timeout() - Replace c_str!() with native Rust C-string literals - Suppress warnings for unread fields - Fix incorrect register name in print statement nouveau: - fix big page table support races in PTE management - improve reclocking on tegra 186+ amdxdna: - fix suspend race conditions - improve handling of zero tail pointers - fix cu_idx overwritten during command setup - enable hardware context priority - remove NPU2 support - update message buffer allocation requirements - update firmware version check ast: - support imported cursor buffers - big endian fixes etnaviv: - add PPU flop reset support imagination: - add AM62P support - introduce hw version checks ivpu: - implement warm boot flow panfrost: - add bo sync ioctl - add GPU_PM_RT support for RZ/G3E SoC panthor: - add bo sync ioctl - enable timestamp propagation - scheduler robustness improvements - VM termination fixes - huge page support rockchip: - RK3368 HDMI Support - get rid of atomic_check fixups - RK3506 support - RK3576/RK3588 improved HPD handling rz-du: - RZ/V2H(P) MIPI-DSI Support v3d: - fix DMA segment size - convert to new logging helpers mediatek: - move DP training to hotplug thread - convert logging to new helpers - add support for HS speed DSI - Genio 510/700/1200-EVK, Radxa NIO-12L HDMI support atmel-hlcdc: - switch to drmm resource - support nomodeset - use newer helpers hisilicon: - fix various DP bugs renesas: - fix kernel panic on reboot exynos: - fix vidi_connection_ioctl using wrong device - fix vidi_connection deref user ptr - fix concurrency regression with vidi_context vkms: - add configfs support for display configuration * tag 'drm-next-2026-02-11' of https://gitlab.freedesktop.org/drm/kernel: (1610 commits) drm/xe/pm: Disable D3Cold for BMG only on specific platforms drm/xe: Fix kerneldoc for xe_tlb_inval_job_alloc_dep drm/xe: Fix kerneldoc for xe_gt_tlb_inval_init_early drm/xe: Fix kerneldoc for xe_migrate_exec_queue drm/xe/query: Fix topology query pointer advance drm/xe/guc: Fix kernel-doc warning in GuC scheduler ABI header drm/xe/guc: Fix CFI violation in debugfs access. accel/amdxdna: Move RPM resume into job run function accel/amdxdna: Fix incorrect DPM level after suspend/resume nouveau/vmm: start tracking if the LPT PTE is valid. (v6) nouveau/vmm: increase size of vmm pte tracker struct to u32 (v2) nouveau/vmm: rewrite pte tracker using a struct and bitfields. accel/amdxdna: Fix incorrect error code returned for failed chain command accel/amdxdna: Remove hardware context status drm/bridge: imx8qxp-pixel-combiner: Fix bailout for imx8qxp_pc_bridge_probe() drm/panel: ilitek-ili9882t: Remove duplicate initializers in tianma_il79900a_dsc drm/i915/display: fix the pixel normalization handling for xe3p_lpd drm/exynos: vidi: use ctx->lock to protect struct vidi_context member variables related to memory alloc/free drm/exynos: vidi: fix to avoid directly dereferencing user pointer drm/exynos: vidi: use priv->vidi_dev for ctx lookup in vidi_connection_ioctl() ...
2026-01-26drm/i915/dsb: move i915 specific DSB buffer implementation to i915Jani Nikula
The DSB buffer implementation is different for both i915 and xe. Move the i915 specific implementation from display to i915 core. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/a01b3e69a3f79713eacf437af00dbe23d2f9c8dd.1768923917.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-01-20docs: kdoc: move kernel-doc to tools/docsJonathan Corbet
kernel-doc is the last documentation-related tool still living outside of the tools/docs directory; the time has come to move it over. [mchehab: fixed kdoc lib location] Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <311d17e403524349940a8b12de6b5e91e554b1f4.1768823489.git.mchehab+huawei@kernel.org>
2026-01-16Merge tag 'drm-intel-next-2026-01-15' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Beyond Display: - Make 'guc_hw_reg_state' static as it isn't exported (Ben) - Fix doc build on mei related interface header (Jani) Display related: - Fix ggtt fb alignment on Xe display (Tvrtko) - More display clean-up towards deduplication and full separation (Jani) - Use the consolidated HDMI tables (Suraj) - Account for DSC slice overhead (Ankit) - Prepare GVT for display modularization (Ankit, Jani) - Enable/Disable DC balance along with VRR DSB (Mitul, Ville) - Protection against unsupported modes in LT PHY (Suraj) - Display W/a addition and fixes (Gustavo) - Fix many SPDX identifier comments (Ankit) - Incorporate Xe3_LPD changes for CD2X divider (Gustavo) - Clean up link BW/DSC slice config computation (Imre) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/aWkNThVRSkGAfUVv@intel.com
2025-12-29drm/i915/display: Add APIs to be used by gvt to get the register offsetsAnkit Nautiyal
GVT code uses macros for register offsets that require display internal structures. This makes clean separation of display code and modularization difficult. Introduce APIs to abstract offset calculations: - intel_display_device_pipe_offset() - intel_display_device_trans_offset() - intel_display_device_cursor_offset() - intel_display_device_mmio_base() These APIs return absolute base offsets for the respective register groups, allowing GVT to compute MMIO addresses without using internal macros or struct fields. This prepares the path to separate display-dependent code from i915/gvt/*. v2: - Build GVT APIs only when GVT is actually enabled. (Jani) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> (#v1) Link: https://patch.msgid.link/20251219060302.2365123-3-ankit.k.nautiyal@intel.com
2025-12-27Merge tag 'drm-intel-next-2025-12-19' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Beyond Display related: - Switch to use kernel standard fault injection in i915 (Juha-Pekka) Display uAPI related: - Display uapi vs. hw state fixes (Ville) - Expose sharpness only if num_scalers is >= 2 (Nemesa) Display related: - More display driver refactor and clean-ups, specially towards separation (Jani) - Add initial support Xe3p_LPD for NVL (Gustavo, Sai, ) - BMG FBC W/a (Vinod) - RPM fix (Dibin) - Add MTL+ platforms to support dpll framework (Mika, Imre) - Other PLL related fixes (Imre) - Fix DIMM_S DRAM decoding on ICL (Ville) - Async flip refactor (Ville, Jouni) - Go back to using AUX interrupts (Ville) - Reduce severity of failed DII FEC enabling (Grzelak) - Enable system cache support for FBC (Vinod) - Move PSR/Panel Replay sink data into intel_connector and other PSR changes (Jouni) - Detect AuxCCS support via display parent interface (Tvrtko) - Clean up link BW/DSC slice config computation(Imre) - Toggle powerdown states for C10 on HDMI (Gustavo) - Add parent interface for PC8 forcewake tricks (Ville) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/aUW3bVDdE63aSFOJ@intel.com
2025-12-26Merge tag 'drm-misc-next-2025-12-12' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for 6.19: UAPI Changes: - panfrost: Add PANFROST_BO_SYNC ioctl - panthor: Add PANTHOR_BO_SYNC ioctl Core Changes: - atomic: Add drm_device pointer to drm_private_obj - bridge: Introduce drm_bridge_unplug, drm_bridge_enter, and drm_bridge_exit - dma-buf: Improve sg_table debugging - dma-fence: Add new helpers, and use them when needed - dp_mst: Avoid out-of-bounds access with VCPI==0 - gem: Reduce page table overhead with transparent huge pages - panic: Report invalid panic modes - sched: Add TODO entries - ttm: Various cleanups - vblank: Various refactoring and cleanups - Kconfig cleanups - Removed support for kdb Driver Changes: - amdxdna: Fix race conditions at suspend, Improve handling of zero tail pointers, Fix cu_idx being overwritten during command setup - ast: Support imported cursor buffers - - panthor: Enable timestamp propagation, Multiple improvements and fixes to improve the overall robustness, notably of the scheduler. - panels: - panel-edp: Support for CSW MNE007QB3-1, AUO B140HAN06.4, AUO B140QAX01.H Signed-off-by: Dave Airlie <airlied@redhat.com> [airlied: fix mm conflict] From: Maxime Ripard <mripard@redhat.com> Link: https://patch.msgid.link/20251212-spectacular-agama-of-abracadabra-aaef32@penduick
2025-12-22drm/{i915, xe}: move initial plane calls to parent interfaceJani Nikula
Add the initial plane handling functions to the display parent interface. Add the call wrappers in dedicated intel_initial_plane.c instead of intel_parent.c, as we'll be refactoring the calls heavily. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/ab91c891677fe2bb83bf5aafa5ee984b2442b84d.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/i915: move display/intel_plane_initial.c to i915_initial_plane.cJani Nikula
intel_plane_initial.c is i915 specific. Move it to i915 core. Start renaming stuff with the slightly more natural "initial plane" rather than "plane initial". Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/cdad733192690a61fbb44921c57fc68cc1cd809f.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-19drm/i915/pc8: Add parent interface for PC8 forcewake tricksVille Syrjälä
We use forcewake to prevent the SoC from actually entering PC8 while performing the PC8 disable sequence. Hide that behind a new parent interface to eliminate the naked forcewake/uncore usage from the display power code. v2: Mark the interface optional and warn if someone calls it when not provided (Jani) Include the header to make sure the extern declaration matches the definition (Jani) v3: Rebase due to shuffling Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251218182052.18756-1-ville.syrjala@linux.intel.com
2025-12-12drm/i915/panic: move i915 specific panic implementation to i915Jani Nikula
The intel_panic.c implementation is i915 specific, and xe has its own. Move it to i915 core as i915_panic.c. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/8dc7af0ae1f859d17b0be269a545146c5536d8fc.1765474612.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-08drm/i915: Use huge tmpfs mountpoint helpersLoïc Molinari
Make use of the new drm_gem_huge_mnt_create() and drm_gem_get_huge_mnt() helpers to avoid code duplication. Now that it's just a few lines long, the single function in i915_gemfs.c is moved into i915_gem_shmem.c. v3: - use huge tmpfs mountpoint in drm_device - move i915_gemfs.c into i915_gem_shmem.c v4: - clean up mountpoint creation error handling v5: - use drm_gem_has_huge_mnt() helper v7: - include <drm/drm_print.h> in i915_gem_shmem.c v8: - keep logging notice message with CONFIG_TRANSPARENT_HUGEPAGE=n - don't access huge_mnt field with CONFIG_TRANSPARENT_HUGEPAGE=n v9: - replace drm_gem_has_huge_mnt() by drm_gem_get_huge_mnt() - remove useless ternary op test in selftests/huge_pages.c v12: - fix layering violation in selftests (Tvrtko) - fix incorrect filename in commit message v13: - add Tvrtko A-b Signed-off-by: Loïc Molinari <loic.molinari@collabora.com> Acked-by: Tvrtko Ursulin <tursulin@ursulin.net> Link: https://patch.msgid.link/20251205182231.194072-6-loic.molinari@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-05Merge drm/drm-next into drm-intel-nextJani Nikula
Backmerge to get the topic/drm-intel-plane-color-pipeline branch contents. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-04drm/i915/color: Create a transfer function color pipelineChaitanya Kumar Borah
Add a color pipeline with three colorops in the sequence 1D LUT - 3x4 CTM - 1D LUT This pipeline can be used to do any color space conversion or HDR tone mapping v2: Change namespace to drm_plane_colorop* v3: Use simpler/pre-existing colorops for first iteration v4: - s/*_tf_*/*_color_* (Jani) - Refactor to separate files (Jani) - Add missing space in comment (Suraj) - Consolidate patch that adds/attaches pipeline property v5: - Limit MAX_COLOR_PIPELINES to 2.(Suraj) Increase it as and when we add more pipelines. - Remove redundant initialization code (Suraj) v6: - Use drm_plane_create_color_pipeline_property() (Arun) Now MAX_COLOR_PIPELINES is 1 Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://patch.msgid.link/20251203085211.3663374-5-uma.shankar@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-04drm/i915: Add intel_color_opChaitanya Kumar Borah
Add data structure to store intel specific details of colorop v2: - Remove dead code - Convert macro to function (Jani) - Remove colorop state as it is not being used - Refactor to separate file Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20251203085211.3663374-3-uma.shankar@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-28drm/i915/hdcp: move i915 specific HDCP GSC implementation to i915Jani Nikula
The HDCP GSC implementation is different for both i915 and xe. Move the i915 specific implementation from display to i915 core. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/d362b256934c6c739d9decda717df2dbc3752481.1764090990.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-21drm/i915: merge soc/intel_gmch.[ch] to display/intel_vga.cJani Nikula
The sole user of the remaining functions in intel_gmch.[ch] is in intel_vga.c. Move everything there. Since intel_gmch.c hasn't been part of xe, use a dummy function relocated from xe_display_misc.c, with #ifdef. This is purely to keep this change non-functional. This allows us to remove soc/intel_gmch.[ch] from i915, compat soc/intel_gmch.h from xe, and xe_display_misc.c from xe. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/b0f853ad7eae686738defa9e8f08a8848df8f226.1763578288.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-21drm/i915/gmch: split out i915_gmch.[ch] from socJani Nikula
Most of the soc/intel_gmch.[ch] code is i915 core specific. Split it out to i915_gmch.[ch]. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/f4f8cc931ef2a5958cebe3ca44d40aedad01626f.1763578288.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-21drm/i915: move intel_rom.[ch] from soc/ to display/Jani Nikula
The sole user of intel_rom.[ch] has always been in display. Move them under display. This allows us to remove the compat soc/intel_rom.h from xe, as well as the Makefile rules to build anything from soc/. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/352ec255a6e9b81c7d1e35d8fbf7018d4049d4d3.1763578288.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-21drm/i915: move intel_dram.[ch] from soc/ to display/Jani Nikula
The remaining users of intel_dram.[ch] are all in display. Move them under display. This allows us to remove the compat soc/intel_dram.h from xe. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/4c0fbdab989a70d287536a7eafb002dc836ced12.1763578288.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-21drm/i915: split out i915_freq.[ch]Jani Nikula
The i915 core only needs three rather specific functions from soc/intel_dram.[ch]: i9xx_fsb_freq(), ilk_fsb_freq(), and ilk_mem_freq(). Add new i915_freq.[ch] and duplicate those functions for i915 to reduce the dependency on soc/ code. Wile duplication in general is bad, here it's a tradeoff to simplify the i915, xe and display interactions. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/7bac1b194afdc20cd45e625a0a32fcbcd0b1136e.1763578288.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-21drm/i915/edram: extract i915_edram.[ch] for edram detectionJani Nikula
While edram detection ostensibly belongs with the rest of the dram stuff in soc/intel_dram.c, it's only required by i915 core, not display. Extract it to a separate i915_edram.[ch] file. This allows us to drop the edram_size_mb member from struct xe_device. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/612edb7b70755655fbf193ba8af1c539fb93b698.1763578288.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-21Merge tag 'v6.18-rc6' into drm-nextDave Airlie
Linux 6.18-rc6 Backmerge in order to merge msm next Signed-off-by: Dave Airlie <airlied@redhat.com>
2025-11-19drm/{i915,xe}/display: move irq calls to parent interfaceJani Nikula
Add an irq parent driver interface for the .enabled and .synchronize calls. This lets us drop the dependency on i915_drv.h and i915_irq.h in multiple places, and subsequently remove the compat i915_irq.h and i915_irq.c files along with the display/ext directory from xe altogether. Introduce new intel_parent.[ch] as the wrapper layer to chase the function pointers and convert between generic and more specific display types. v2: Keep static wrappers in intel_display_irq.c (Ville) v3: Full blown wrappers in intel_parent.[ch] (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/dd62dd52ef10d9ecf77da3bdf6a70f71193d141c.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-08kbuild: Let kernel-doc.py use PYTHON3 overrideJean Delvare
It is possible to force a specific version of python to be used when building the kernel by passing PYTHON3= on the make command line. However kernel-doc.py is currently called with python3 hard-coded and thus ignores this setting. Use $(PYTHON3) to run $(KERNELDOC) so that the desired version of python is used. Signed-off-by: Jean Delvare <jdelvare@suse.de> Reviewed-by: Nicolas Schier <nsc@kernel.org> Reviewed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://patch.msgid.link/20251107192933.2bfe9e57@endymion Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2025-11-07drm/i915/frontbuffer: Fix intel_frontbuffer lifetime handlingVille Syrjälä
The current attempted split between xe/i915 vs. display for intel_frontbuffer is a mess: - the i915 rcu leaks through the interface to the display side - the obj->frontbuffer write-side is now protected by a display specific spinlock even though the actual obj->framebuffer pointer lives in a i915 specific structure - the kref is getting poked directly from both sides - i915_active is still on the display side Clean up the mess by moving everything about the frontbuffer lifetime management to the i915/xe side: - the rcu usage is now completely contained in i915 - frontbuffer_lock is moved into i915 - kref is on the i915/xe side (xe needs the refcount as well due to intel_frontbuffer_queue_flush()->intel_frontbuffer_ref()) - the bo (and its refcounting) is no longer on the display side - i915_active is contained in i915 I was pondering whether we could do this in some kind of smaller steps, and perhaps we could, but it would probably have to start with a bunch of reverts (which for sure won't go cleanly anymore). So not convinced it's worth the hassle. Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251016185408.22735-10-ville.syrjala@linux.intel.com
2025-11-01drm/i915/ltphy: Phy lane reset for LT PhySuraj Kandpal
Define function to bring phy lane out of reset for LT Phy and the corresponding pre-requisite steps before we follow the steps for Phy lane reset. Also create a skeleton of LT PHY PLL enable sequence function in which we can place this function Bspec: 77449, 74749, 74499, 74495, 68960 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-4-suraj.kandpal@intel.com
2025-10-31drm/i915/display: add intel_display_run_as_guest()Jani Nikula
Add intel_display_utils.c for display utilities that need more than a header. Start off with intel_display_run_as_guest(). The implementation is intentional duplication of the i915_utils.h i915_run_as_guest(), with the idea that it's small enough to not matter. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patch.msgid.link/469f9c41e0c3e3099314a3cf1a7671bf36ec8ffd.1761146196.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-30drm/i915/display: Add CASF strength and winsizeNemesa Garg
Add register definitions for sharpness strength and filter window size used by CASF. Provide functions to read and write these fields. The sharpness strength value is determined by user input, while the winsize is based on the resolution. The casf_enable flag should be set if the platform supports sharpness adjustments and the user API strength is not zero. Once sharpness is enabled, update the strength bit of the register whenever the user changes the strength value, as the enable bit and winsize bit remain constant. Introduce helper to enable, disable and update strength. Add relavant strength and winsize in both enable and disable. v2: Introduce get_config for casf[Ankit] v3: Replace 0 with FILTER_STRENGTH_MASK[Ankit] v4: After updating strength add win_sz register v5: Replace u16 with u32 for total_pixel v6: Add casf logging v7: Add helper for enable and disable casf Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251028120747.3027332-4-ankit.k.nautiyal@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-17drm/i915/bw: Untangle dbuf bw from the sagv/mem bw stuffVille Syrjälä
Currently intel_bw.c contains basically three completely independent parts: - SAGV/memory bandwidth handling - DBuf bandwidth handling - "Maximum pipe read bandwidth" calculation, which is some kind of internal per-pipe bandwidth limit. Carve out the DBuf bandwdith handling into a separate file since there is no actual dependency between it and the rest of intel_bw.c. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20251013201236.30084-2-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2025-10-16drm/i915: move and rename reg_in_range_tableMatt Atwood
reg_in_range_table is a useful function that is used in multiple places, and will be needed for WA_BB implementation later. Let's move this function and i915_range struct to its own file, as we are trying to move away from i915_utils files. v2: move functions to their own file v3: use correct naming convention Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://lore.kernel.org/r/20251009215210.41000-1-matthew.s.atwood@intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-10-16drm/i915/prefill: Introduce skl_prefill.cVille Syrjälä
Add a new helper thingy to deal with the pipe prefill latency. We get three potentially useful thigns out of this: - skl_prefill_vblank_too_short() used for checking the actual vblank/guardband length - skl_prefill_min_guardband() to calculate a suitable guardband size based on some worst case scaling/etc. estimates - skl_prefill_min_cdclk() used to calculate a minimum cdclk frequency required for very small vblank lengths (in case the otherwise computed minimum cdclk doesn't result in fast enough prefill). The internal arithmetic is done terms of scanlines using .16 binary fixed point representation. v2: Add the missing <<16 for framestart_delay Drop the cdclk_state stuff in favor of crtc_state->min_cdclk Rename to skl_prefill since this is skl+ only Use intel_crtc_vblank_length() instead of hand rolling it memset(0) in prefill_init() Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20251014191808.12326-9-ville.syrjala@linux.intel.com
2025-10-09drm/i915: Disable tracepoints for PREEMPT_RTMaarten Lankhorst
Luca Abeni reported this: | BUG: scheduling while atomic: kworker/u8:2/15203/0x00000003 | CPU: 1 PID: 15203 Comm: kworker/u8:2 Not tainted 4.19.1-rt3 #10 | Call Trace: | rt_spin_lock+0x3f/0x50 | gen6_read32+0x45/0x1d0 [i915] | g4x_get_vblank_counter+0x36/0x40 [i915] | trace_event_raw_event_i915_pipe_update_start+0x7d/0xf0 [i915] The tracing events use trace_intel_pipe_update_start() among other events use functions acquire spinlock_t locks which are transformed into sleeping locks on PREEMPT_RT. A few trace points use intel_get_crtc_scanline(), others use ->get_vblank_counter() wich also might acquire a sleeping locks on PREEMPT_RT. At the time the arguments are evaluated within trace point, preemption is disabled and so the locks must not be acquired on PREEMPT_RT. Based on this I don't see any other way than disable trace points on PREMPT_RT. [mlankhorst] The original patch was insufficient, and since the tracing infrastructure does not allow for partial disabling of tracepoints. Completely disable tracing for the entire i915 driver in PREEMPT_RT, a separate fix for display tracepoints on xe is added to make those work. Cc: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reported-by: Luca Abeni <lucabe72@gmail.com> Cc: Steven Rostedt <rostedt@goodmis.org> Co-developed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250828090944.101069-1-dev@lankhorst.se Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
2025-09-17drm/i915: split out vlv_clock.[ch]Jani Nikula
Move the VLV clock related functions to their own file. v2: Rebase Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> # v1 Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/0bc4a930f3e364c4fc37479f56bf07ccee854fcc.1757688216.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-09-12drm/i915: split out i915_timer_util.[ch]Jani Nikula
Move timer related utilities from i915_utils.[ch] to separate new files i915_timer_util.[ch]. Clean up related includes. Note: Arguably none of this should exist in i915 in the first place. At least isolate it better. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/0a83d9489626121dcefcd4c1a05317399b5708f3.1757582214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-09-08drm/{i915,xe}/panic: split out intel_panic.[ch]Jani Nikula
intel_bo.[ch] is not the appropriate location for the panic functionality. Split out intel_panic.[ch] and xe_panic.c in i915 and xe. Keep the function names for now. Cc: Jocelyn Falempe <jfalempe@redhat.com> Cc: Maarten Lankhorst <dev@lankhorst.se> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://lore.kernel.org/r/d98b831a011a028ffd33ce99b0ba62be061ee235.1756835342.git.jani.nikula@intel.com
2025-06-27drm/i915/flipq: Provide the nuts and bolts code for flip queueVille Syrjälä
Provide the lower level code for PIPEDMC based flip queue. We'll use the so called semi-full flip queue mode where the PIPEDMC will start the provided DSB on a scanline a little ahead of the vblank. We need to program the triggering scanline early enough so that the DSB has enough time to complete writing all the double buffered registers before they get latched (at start of vblank). The firmware implements several queues: - 3 "plane queues" which execute a single DSB per entry - 1 "general queue" which can apparently execute 2 DSBs per entry - 1 vestigial "fast queue" that replaced the "simple flip queue" on ADL+, but this isn't supposed to be used due to issues. But we only need a single plane queue really, and we won't actually use it as a real queue because we don't allow queueing multiple commits ahead of time. So the whole thing is perhaps useless. I suppose there migth be some power saving benefits if we would get the flip scheduled by userspace early and then could keep some hardware powered off a bit longer until the DMC kicks off the flipq programming. But that is pure speculation at this time and needs to be proven. The code to hook up the flip queue into the actual atomic commit path will follow later. TODO: need to think how to do the "wait for DMC firmware load" nicely need to think about VRR and PSR etc. v2: Don't write DMC_FQ_W2_PTS_CFG_SEL on pre-lnl Don't oops at flipq init if there is no dmc v3: Adapt to PTL+ flipq changes (different queue entry layout, different trigger event, need VRR TG) Use the actual CDCLK frequency Ask the DSB code how long things are expected to take v3: Adjust the cdclk rounding (docs are 100% vague, Windows rounds like this) Initialize some undocumented magic DMC variables on PTL v4: Use PIPEDMC_FQ_STATUS for busy check (the busy bit in PIPEDMC_FQ_CTRL is apparently gone on LNL+) Based the preempt timeout on the max exec time Preempt before disabling the flip queue Order the PIPEDMC_SCANLINECMP* writes a bit more carefully Fix some typos v5: Try to deal with some clang-20 div-by-zero false positive (Nathan) Add some docs (Jani) Cc: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> epr Link: https://patchwork.freedesktop.org/patch/msgid/20250624170049.27284-5-ville.syrjala@linux.intel.com
2025-06-19drm/i915/plane: rename intel_atomic_plane.[ch] to intel_plane.[ch]Jani Nikula
It's all atomic, no need to emphasize this. v2: Also update Documentation/gpu/i915.rst (Gustavo) Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/ba5f304e9fe71723191d872e6828d461e1a572bd.1750147992.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-07-20 17:32:42 +0000