linux.git - Linux kernel source tree

Age	Commit message (Expand)	Author
12 days	Merge branches 'clk-pile' and 'clk-microchip' into clk-next	Stephen Boyd
2026-08-17	Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile	Stephen Boyd
2026-08-06	clk: renesas: Add R-Car X5H CPG driver	Geert Uytterhoeven
2026-08-05	Merge tag 'renesas-r8a78000-dt-binding-defs-tag2' into renesas-clk-for-v7.3	Geert Uytterhoeven
2026-07-13	clk: r9a08g045: Add clocks and resets for CAN-FD	Claudiu Beznea
2026-07-03	Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c f...	Uwe Kleine-König (The Capable Hub)
2026-06-30	clk: renesas: r9a09g047: Add LVDS clocks and resets	Tommaso Merciai
2026-06-30	clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display p...	Lad Prabhakar
2026-06-30	clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library	Lad Prabhakar
2026-06-30	clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations	Lad Prabhakar
2026-06-30	clk: renesas: r9a08g046: Add USB2.0 clock and reset entries	Biju Das
2026-06-30	clk: renesas: r9a09g077: Add RTC clocks	Lad Prabhakar
2026-06-30	clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC ...	Lad Prabhakar
2026-06-30	clk: renesas: r9a08g046: Add clock and reset entries for GE3D	Biju Das
2026-06-30	clk: renesas: r9a08g046: Add clock and reset entries for SDHI	Biju Das
2026-06-30	clk: renesas: r9a09g047: Add audio clock and reset support	John Madieu
2026-06-29	clk: renesas: rzg2l-cpg: use clk_determine_rate_noop()	Brian Masney
2026-05-28	clk: renesas: r9a08g045: Drop unused pm_domain header file	Biju Das
2026-05-28	clk: renesas: r8a779g0: Add DSC clock	Marek Vasut
2026-05-25	clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowing	Lad Prabhakar
2026-05-25	clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macro	Lad Prabhakar
2026-05-22	clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed ones	Biju Das
2026-05-22	clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro	Biju Das
2026-05-22	clk: renesas: rzg2l: Simplify SAM PLL configuration macro	Biju Das
2026-05-15	clk: renesas: r8a73a4: Add ZT/ZTR trace clocks	Marek Vasut
2026-05-11	clk: renesas: r9a08g046: Add RSPI clocks and resets	Biju Das
2026-05-11	clk: renesas: r9a08g046: Add SSIF-2 clocks and resets	Biju Das
2026-05-11	clk: renesas: r9a08g046: Add RSCI clocks and resets	Biju Das
2026-05-07	clk: renesas: cpg-mssr: Add number of clock cells check	Geert Uytterhoeven
2026-05-07	clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()	Geert Uytterhoeven
2026-05-07	clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()	Geert Uytterhoeven
2026-05-07	clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocks	Biju Das
2026-05-04	Merge tag 'clk-renesas-rzg3e-plldsi-tag' into renesas-clk-for-v7.2	Geert Uytterhoeven
2026-05-04	clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets	Tommaso Merciai
2026-05-04	clk: renesas: r9a09g047: Add support for DSI clocks and resets	Tommaso Merciai
2026-05-04	clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK	Tommaso Merciai
2026-05-04	clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks	Tommaso Merciai
2026-05-04	clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks	Tommaso Merciai
2026-05-04	clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks	Tommaso Merciai
2026-05-04	clk: renesas: r9a09g047: Add CLK_PLLETH_LPCLK support	Tommaso Merciai
2026-05-04	clk: renesas: rzv2h: Add PLLDSI clk mux support	Tommaso Merciai
2026-04-27	clk: renesas: r8a7740: Add ZT/ZTR trace clocks	Marek Vasut
2026-04-27	clk: renesas: r9a09g077: Add MTU3 module clock	Cosmin Tanislav
2026-04-27	clk: renesas: r9a08g046: Add I2C clocks and resets	Biju Das
2026-04-27	clk: renesas: r9a08g046: Add SCIF{1..5} clocks and resets	Biju Das
2026-04-27	clk: renesas: r9a08g046: Add WDT clocks and reset	Biju Das
2026-04-27	clk: renesas: r9a08g046: Add CA55 core clocks	Biju Das
2026-04-27	clk: renesas: r9a08g046: Add GPIO clocks/resets	Biju Das
2026-04-27	clk: renesas: r9a08g046: Add GBETH clocks and resets	Biju Das
2026-04-27	clk: renesas: r8a08g046: Add support for PLL6	Biju Das