| Age | Commit message (Expand) | Author |
|---|
| 2015-03-31 | MIPS: idle: Workaround wait + FDC problems | James Hogan |
| 2015-03-31 | MIPS: Read CPU IRQ line that FDC to routed to | James Hogan |
| 2015-03-31 | MIPS: Add arch CDMM definitions and probing | James Hogan |
| 2015-03-31 | MIPS: Allow shared IRQ for timer & perf counter | James Hogan |
| 2015-03-31 | MIPS: perf: Allow sharing IRQ with timer | James Hogan |
| 2015-03-31 | MIPS: cevt-r4k: Cleanup c0_compare_interrupt. | Ralf Baechle |
| 2015-03-31 | MIPS: cevt-r4k: Make interrupt handler shared | James Hogan |
| 2015-03-31 | MIPS: Remove redundant IPTI==IPPCI logic | James Hogan |
| 2015-03-31 | MIPS: cevt-r4k: Use CAUSEF_TI, CAUSEF_PCI constants | James Hogan |
| 2015-03-31 | MIPS: cevt-r4k: Move handle_perf_irq() out of header | James Hogan |
| 2015-03-27 | MIPS: KVM: Add base guest MSA support | James Hogan |
| 2015-03-27 | MIPS: KVM: Add base guest FPU support | James Hogan |
| 2015-03-27 | MIPS: Clear [MSA]FPE CSR.Cause after notify_die() | James Hogan |
| 2015-03-27 | Revert "MIPS: Don't assume 64-bit FP registers for context switch" | James Hogan |
| 2015-03-27 | MIPS: prevent FP context set via ptrace being discarded | Paul Burton |
| 2015-03-27 | MIPS: Ensure FCSR cause bits are clear after invoking FPU emulator | Paul Burton |
| 2015-03-27 | MIPS: clear MSACSR cause bits when handling MSA FP exception | Paul Burton |
| 2015-03-27 | MIPS: Push .set mips64r* into the functions needing it | Paul Burton |
| 2015-03-24 | mips: copy_thread(): rename 'arg' argument to 'kthread_arg' | Alex Dowad |
| 2015-03-19 | MIPS: Add support for XPA. | Steven J. Hill |
| 2015-03-05 | mips: fix up obsolete cpu function usage. | Rusty Russell |
| 2015-02-21 | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus | Linus Torvalds |
| 2015-02-20 | MIPS: OCTEON: Delete unused COP2 saving code | Aleksey Makarov |
| 2015-02-20 | MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register | Chandrakala Chavva |
| 2015-02-20 | MIPS: OCTEON: Save and restore CP2 SHA3 state | David Daney |
| 2015-02-20 | MIPS: OCTEON: Fix FP context save. | David Daney |
| 2015-02-20 | MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs | David Daney |
| 2015-02-20 | MIPS: Add set/clear CP0 macros for PageGrain register | Steven J. Hill |
| 2015-02-19 | Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/... | Ralf Baechle |
| 2015-02-19 | MIPS: Export MSA functions used by lose_fpu(1) for KVM | James Hogan |
| 2015-02-19 | MIPS: Export FP functions used by lose_fpu(1) for KVM | James Hogan |
| 2015-02-17 | MIPS: kernel: elf: Improve the overall ABI and FPU mode checks | Markos Chandras |
| 2015-02-17 | MIPS: kernel: process: Do not allow FR=0 on MIPS R6 | Markos Chandras |
| 2015-02-17 | MIPS: Make use of the ERETNC instruction on MIPS R6 | Markos Chandras |
| 2015-02-17 | MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6 | Leonid Yegoshin |
| 2015-02-17 | MIPS: Add LLB bit and related feature for the Config 5 CP0 register | Markos Chandras |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions | Markos Chandras |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions | Markos Chandras |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 BALC instruction | Markos Chandras |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions | Markos Chandras |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions | Markos Chandras |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 branch compact (BC) instruction | Markos Chandras |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions | Markos Chandras |
| 2015-02-17 | MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructions | Markos Chandras |
| 2015-02-17 | MIPS: Emulate the BC1{EQ,NE}Z FPU instructions | Markos Chandras |
| 2015-02-17 | MIPS: kernel: branch: Do not emulate the branch likelies on MIPS R6 | Markos Chandras |
| 2015-02-17 | MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6 | Markos Chandras |
| 2015-02-17 | MIPS: kernel: syscall: Set the appropriate ISA level for MIPS R6 | Markos Chandras |
| 2015-02-17 | MIPS: kernel: unaligned: Add support for the MIPS R6 | Leonid Yegoshin |
| 2015-02-17 | MIPS: kernel: cps-vec: Replace "addi" with "addiu" | Markos Chandras |
