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2026-08-19Merge tag 'spi-v7.3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "Along with a lot of driver specific work we've got a couple of core features here. The bigger one is that we've now got support for instantiating devices from sysfs similarly to how it's already done for I2C, this is used with development boards with non-enumerable expansion headers since SPI devices need to be manually specified. We also have support for the DQS signal on higher end flash devices. - Support for instantiating devices from sysfs, useful for development boards with non-enumerable plugin modules, from Vishwaroop A. - Support for DQS in spi-mem, an additional signal used by flash devices to avoid clock skew from Miquel Raynal. - Support for more advanced SPI modes on DesignWare controllers from Sudip Mukherjee. - Changes from Jisheng Zhang to update to modern methods of specifying the PM callbacks. - Fixes for DMA mapping error handling, plus KUnit tests for this, from Honghui Jiang. - Substantial cleanup and performance work in the nxp-spi driver. - Support for Microchip LAN969x, Nuvoton MA35D1 QSPI, Qualcomm SA8255p and SA8797P, and StarFive JHB100 SFC" * tag 'spi-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (132 commits) spi: Add KUnit coverage for DMA mapping error paths spi: Clear current DMA devices when unmapping a message spi: Move __spi_unmap_msg() before __spi_map_msg() spi: Fix DMA mapping ownership on partial map failure spi: dt-bindings: sun6i: Add compatibles for A733's SPI controllers spi: ma35d1-qspi: Use the existing update helper spi: ma35d1-qspi: Add DTR support spi: ma35d1-qspi: Allow several command bytes spi: ma35d1-qspi: Move speed setting to bus configuration spi: ma35d1-qspi: Remove redundant reset operation spi: dw: Remove shadowed dws in dw_spi_setup() spi: img-spfi: don't disable runtime PM on DMA deferred probe spi: mtk-nor: Propagate errors from IRQ request spi: mtk-nor: Propagate errors from optional IRQ lookup spi: spi-qpic-snand: Handle Macronix quad read opcode 0x6b spi: spi-qpic-snand: add quad mode support spi: spi-qpic-snand: move command mapping helper spi: hisi-sfc-v3xx: Propagate errors from optional IRQ lookup spi: meson-spifc: use devm_pm_runtime_set_active_enabled spi: sprd-adi: Fix probe succeeding without registering the controller ...
2026-08-14spi: dt-bindings: sun6i: Add compatibles for A733's SPI controllersJerome Brunet
The A733 has six SPI controllers with the same IP as the A523. Like the A523, one of them (spi1) also supports DBI mode. Add SoC specific compatible strings, falling back to the A523 ones. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://patch.msgid.link/20260812-allwinner-a733-spi-support-v2-1-937bff0fa78e@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-06spi: dt-bindings: snps,dw-apb-ssi: Document Axiado AX3005Swark Yang
The Axiado AX3005 SPI controller is software-compatible with the Synopsys DesignWare APB SSI 1.01a programming interface. Document the "axiado,ax3005-spi" SoC-specific compatible with "snps,dwc-ssi-1.01a" as its fallback. This preserves identification of the AX3005 integration while allowing the controller to use the existing DesignWare APB SSI support. Signed-off-by: Swark Yang <syang@axiado.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260805-upstrea-ax3005-spi-v4-v4-1-5b8bc11cb841@axiado.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-04spi: Few cleanups while looking at num-csMark Brown
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> says: Few minor cleanups for DT bindings and Andes driver. Patches do not have inter-dependencies. Link: https://patch.msgid.link/20260804-spi-num-cs-v1-0-4ccb13dcc7b0@oss.qualcomm.com
2026-08-04spi: dt-bindings: spi-cadence: Drop duplicated type/refKrzysztof Kozlowski
spi-controller.yaml schema already defines this $ref for this property, so binding does not have to. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260804-spi-num-cs-v1-4-4ccb13dcc7b0@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-04spi: dt-bindings: axiado,ax3000-spi: Drop duplicated type/refKrzysztof Kozlowski
spi-controller.yaml schema already defines this $ref for this property, so binding does not have to. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260804-spi-num-cs-v1-3-4ccb13dcc7b0@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-04spi: dt-bindings: marvell,armada-3700-spi: Drop redundant num-csKrzysztof Kozlowski
'num-cs' property is a single integer, thus the binding should not set maxItems. This could be replaced with proper min/max constraints for values, except that such constraints are not known. spi-controller.yaml schema already defines this property, so its presence here is redundant. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260804-spi-num-cs-v1-2-4ccb13dcc7b0@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-04spi: dt-bindings: andestech,ae350-spi: Drop redundant num-csKrzysztof Kozlowski
'num-cs' property is a single integer, thus the binding should not set maxItems. This could be replaced with proper min/max constraints for values, except that hardware (as expressed in driver) supports only one native chipselect, thus constraint of "const:1" would make the property implied by the compatible. spi-controller.yaml schema already defines this property, so its presence here is redundant. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260804-spi-num-cs-v1-1-4ccb13dcc7b0@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-04spi: Add support for StarFive JHB100 SFCMark Brown
Changhuang Liang <changhuang.liang@starfivetech.com> says: This serial add support for the StarFive JHB100 SoC SPI Flash Controller (SFC), which is based on the Synopsys DesignWare SSI version 2.00a but with some customizations and it also add enhanced SPI for DesignWare SPI controllers. I picked up some patches from series [1]. This series depends on the series [2]: [1] https://lore.kernel.org/all/20221212180732.79167-1-sudip.mukherjee@sifive.com/ [2] https://lore.kernel.org/all/20260521012932.24163-1-changhuang.liang@starfivetech.com/ v1: https://lore.kernel.org/all/20260709055204.138168-1-changhuang.liang@starfivetech.com/ Link: https://patch.msgid.link/20260803124044.156998-1-changhuang.liang@starfivetech.com
2026-08-04spi: dt-bindings: snps,dw-apb-ssi: Add starfive,jhb100-sfcChanghuang Liang
Add a new compatible string "starfive,jhb100-sfc" for the StarFive JHB100 SPI Flash Controller, it based on the Synopsys DesignWare SSI version 2.00a but with minor modifications. Due to these minor modifications, it only supports access for flash memory and requires a system controller register to configure the address mode filter for SPI NOR flash devices. The starfive,sfc-filter-syscon property is required to provide a phandle to the system controller that manages switching between 3-byte and 4-byte addressing modes, essential for supporting SPI NOR flash devices with different address width requirements. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260803124044.156998-11-changhuang.liang@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-08-03spi: dt-bindings: nuvoton,ma35d1-qspi: Disallow GPIO chip selectsChi-Wen Weng
The generic SPI controller binding allows GPIO-based chip selects, but the MA35D1 QSPI driver currently supports only the controller's native chip selects. Disallow the cs-gpios property so that the binding matches the functionality provided by the driver. Signed-off-by: Chi-Wen Weng <cwweng@nuvoton.com> Link: https://patch.msgid.link/20260803024048.1641756-1-cwweng.linux@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-07-31spi: ma35d1-qspi: Add Nuvoton MA35D1 QSPI controllerMark Brown
Chi-Wen Weng <cwweng.linux@gmail.com> says: Add devicetree binding and SPI controller driver support for the Quad SPI controller found in Nuvoton MA35D1 SoCs. The controller provides two native chip selects and supports standard SPI and spi-mem operations using single, dual and quad bus widths. This initial implementation uses 8-bit PIO transfers and supports per-operation clock configuration, clock and reset handling, and direct execution of SPI memory operations. DMA and active-high chip select support are intentionally left out of the initial driver. Link: https://patch.msgid.link/20260731023818.1626075-1-cwweng.linux@gmail.com
2026-07-31dt-bindings: spi: nuvoton,ma35d1-qspi: Add Nuvoton MA35D1 QSPIChi-Wen Weng
Add a devicetree binding for the Quad SPI controller found in Nuvoton MA35D1 SoCs. The controller supports SPI memory devices such as SPI NOR and SPI NAND flashes. It has one register range, one clock input and one reset line, and supports up to two chip selects. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Chi-Wen Weng <cwweng@nuvoton.com> Link: https://patch.msgid.link/20260731023818.1626075-2-cwweng.linux@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-07-29spi: Merge up fixesMark Brown
The SpacemiT driver fixes and new work collide with each other.
2026-07-27spi: dt-bindings: qcom,sa8255p-geni-spi: Add compatible for Nord SA8797PShawn Guo
Document Nord SA8797P QUP GENI SPI controller, which is compatible with SA8255P controller. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260714120226.1788391-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-07-23spi: dt-bindings: nxp,imx94-xspi: add DMA propertiesHan Xu
Add dmas and dma-names to describe TX and RX DMA channels for the i.MX94 XSPI controller. Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Han Xu <han.xu@nxp.com> Link: https://patch.msgid.link/20260722-xspi_dma_upstream-v3-1-6b7ff50cae8e@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-07-21spi: dt-bindings: spacemit: add K3 SPI compatibleZhengyu He
The K3 SPI controller is compatible with K1, so allow K3 device trees to use "spacemit,k1-spi" as fallback. Signed-off-by: Cody Kang <cody.kang.hk@outlook.com> Signed-off-by: Zhengyu He <hezhy472013@gmail.com> Link: https://patch.msgid.link/20260717-k3-com260-spi-v7-2-rc2-b4-preview-20260716-v1-2-969a1b0f783f@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-07-19spi: atmel-quadspi: add support for LAN969xMark Brown
Robert Marko <robert.marko@sartura.hr> says: This series adds QSPI support for the Microchip LAN969x which has two QSPI controllers based on SAMA7G5. It requires pad calibration, supports DMA, and supports 100 MHz operation. It requires a different init sequence to SAMA7G5 so support for custom .init per controller caps is added, and existing controllers relying on checking gclk are converted to it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://patch.msgid.link/20260709112006.390742-1-robert.marko@sartura.hr
2026-07-19spi: dt-bindings: Document LAN969x QSPIRobert Marko
LAN969x has 2 QSPI instances, so document their compatible. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://patch.msgid.link/20260709112006.390742-2-robert.marko@sartura.hr Signed-off-by: Mark Brown <broonie@kernel.org>
2026-07-06spi: Enable SPI on SA8255p Qualcomm platformsMark Brown
Praveen Talari <praveen.talari@oss.qualcomm.com> says: The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The driver requests resources operations over SCMI using power and performance protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power states(on/off). The SCMI performance protocol manages SPI frequency, with each frequency rate represented by a performance level. The driver uses geni_se_set_perf_opp() API to request the desired frequency rate. As part of geni_se_set_perf_opp(), the OPP for the requested frequency is obtained using dev_pm_opp_find_freq_floor() and the performance level is set using dev_pm_opp_set_opp(). Link: https://patch.msgid.link/20260618-enable-spi-on-sa8255p-v4-0-f5b5067e7e1e@oss.qualcomm.com
2026-07-06spi: dt-bindings: describe SA8255pPraveen Talari
Add DT bindings for the QUP GENI SPI controller on sa8255p platform. SA8255p platform abstracts resources such as clocks, interconnect and GPIO pins configuration in Firmware. SCMI power and perf protocols are utilized to request resource configurations. SA8255p platform does not require the Serial Engine (SE) common properties as the SE firmware is loaded and managed by the TrustZone (TZ) secure environment. Co-developed-by: Nikunj Kela <quic_nkela@quicinc.com> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Link: https://patch.msgid.link/20260618-enable-spi-on-sa8255p-v4-1-f5b5067e7e1e@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-07-05Merge tag 'spi-fix-v7.2-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A small set of fixes that came in since -rc1, we have one core fix for shutting down target mode properly if the system suspends while it's running plus a small set of fairly unremarkable device specific fixes. There's also a couple of pure DT binding changes for Renesas SoCs, the power domains one allows some SoCs to be correctly described with existing code" * tag 'spi-fix-v7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: rzv2h-rspi: Fix DMA transfer error handling for signal interruption spi: dt-bindings: snps,dw-apb-ssi: add 'power-domains' property spi: dt-bindings: snps,dw-apb-ssi: drop superfluous RZ/N1 entry spi: dw: use the correct error msg if request_irq() fails spi: dw: fix first spi transfer with dma always fallback to PIO spi: core: Abort active target transfer on controller suspend spi: sh-msiof: abort transfers when reset times out
2026-06-30spi: dt-bindings: snps,dw-apb-ssi: add 'power-domains' propertyWolfram Sang
This SPI controller likely belongs to a power domain for all the SoCs listed. For sure, it belongs to one on the Renesas RZ/N1 SoC, so enable the property to be able to describe its power domain in DTs. Suggested-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Herve Codina <herve.codina@bootlin.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260626180326.9593-3-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-06-30spi: dt-bindings: snps,dw-apb-ssi: drop superfluous RZ/N1 entryWolfram Sang
Commit 164c05f03ffa ("spi: Convert DW SPI binding to DT schema") added an RZ/N1 entry which was not in the original txt-file. It doesn't follow the usual "<soc entry>, <soc family entry>" style for Renesas SoCs which was properly added later with commit 029d32a892a8 ("spi: dw-apb-ssi: Integrate Renesas RZ/N1 SPI controller"). In that commit, removing the bogus entry was overlooked and is finally done now. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260626180326.9593-2-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-06-29spi: dt-bindings: st,stm32-qspi: Add power-domains propertyPatrice Chotard
STM32 QSPI may be in a power domain. Allow a single 'power-domains' entry for STM32 QSPI. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260618-add_power_domain_for_qpsi-v1-1-4d7e57bcfb9a@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-06-29spi: dt-bindings: octeon: Convert to DT schemaNinad Naik
Convert octeon-3010 to DT schema Signed-off-by: Ninad Naik <ninadnaik07@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260618180149.475658-1-ninadnaik07@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-06-26Merge tag 'spi-fix-v7.2-merge-window' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A fairly unremarkable collection of fixes that came in over the merge window, plus a new device ID for the DesignWare controller in the StarFive JHB100 SoC. There's a couple of core fixes included, one avoiding freeing an empty resource in error handling cases and another which fixes a NULL dereference which could be triggered by using an abnormal device registration flow like driver_override" * tag 'spi-fix-v7.2-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: imx: reconfigure for PIO when DMA cannot be started spi: dw: Add support for snps,dwc-ssi-2.00a spi: dt-bindings: snps,dw-apb-ssi: Add starfive,jhb100-spi spi: rpc-if: Use correct device for hardware reinitialization on resume spi: acpi: Free resource list at appropriate time spi: dw: fix wrong BAUDR setting after resume spi: uniphier: Fix completion initialization order before devm_request_irq() spi: Add NULL check for spi_get_device_id() in spi_get_device_match_data()
2026-06-19spi: dt-bindings: snps,dw-apb-ssi: Add starfive,jhb100-spiChanghuang Liang
Add a new compatible string "starfive,jhb100-spi" for the StarFive JHB100 SPI, it based on the Synopsys DesignWare SSI version 2.00a, uses snps,dwc-ssi-2.00a as the primary fallback and snps,dwc-ssi-1.01a as the secondary fallback. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260619143443.22267-2-changhuang.liang@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-06-17Merge tag 'devicetree-for-7.2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DT core: - Add support for handling multiple cells in "iommu-map" entries - Support only 1 entry in /reserved-memory "reg" entries. Support for more than 1 entry has been broken - Fix a UAF on alloc_reserved_mem_array() failure - Make "ibm,phandle" handling logic specific to PPC - Use memcpy() instead of strcpy() for known length strings - Ensure __of_find_n_match_cpu_property() handles malformed "reg" entries - Add various checks that expected strings are strings before accessing them - Drop redundant memset() when unflattening DT DT bindings: - Add a DTS style checker. Currently hooked up to dt_binding_check to check examples - Convert st,nomadik platform, ti,omap-dmm, and ti,irq-crossbar bindings to DT schema - Add Apple System Management Controller hwmon, Qualcomm Hamoa Embedded Controller, Qualcomm IPQ6018 PWM controller, fsl,mc1323, Samsung SOFEF01-M DDIC panel, Freescale i.MX53 Television Encoder, Samsung S2M series PMIC extcon, and MT6365 PMIC AuxADC schemas - Extend bindings for QCom Maili and Nord PDC, QCom Hali fastrpc, qcom,eliza-imem, qcom,oryon-1-5 CPU, and MT6365 Keys - Consolidate "sram" property definitions - Fix constraints on "nvmem" properties which only contain phandles and no arg cells - Another pass of fixing "phandle-array" constraints - Add Gira vendor prefix" * tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (50 commits) dt-bindings: interrupt-controller: qcom,pdc: Add Maili compatible string dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schema dt-bindings: vendor-prefixes: add Gira dt-bindings: embedded-controller: Add Qualcomm reference device EC description dt-bindings: pwm: add IPQ6018 binding dt-bindings: hwmon: Add Apple System Management Controller hwmon schema docs: dt: writing-schema: Clarify what is required in a schema of: Respect #{iommu,msi}-cells in maps of: Factor arguments passed to of_map_id() into a struct of: Add convenience wrappers for of_map_id() of: reserved_mem: zero total_reserved_mem_cnt if no valid /reserved-memory entry of: reserved_mem: handle NULL name in of_reserved_mem_lookup() dt-bindings: cache: l2c2x0: Add missing power-domains dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example dt-bindings: nvmem: consumer: Make 'nvmem' an array of one-item entries drivers/of/overlay: Use memcpy() to copy known length strings dt-bindings: add self-test fixtures for style checker dt-bindings: wire style checker into dt_binding_check scripts/jobserver-exec: propagate child exit status dt-bindings: add DTS style checker ...
2026-06-10spi: dt-bindings: nuvoton,npcm750-fiu: Convert to DT schemaTomer Maimon
Convert the Nuvoton NPCM FIU binding to DT schema format. Document the required control registers and the optional direct- mapped flash window separately, matching the driver behavior when the direct mapping is not described. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260609163919.3321228-4-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-06-01spi: fsl-lpspi: fix DMA termination issuesMark Brown
Carlos Song (OSS) <carlos.song@oss.nxp.com> says: This series fixes two issues in the fsl-lpspi DMA transfer error paths. Patch 1 replaces the deprecated dmaengine_terminate_all() with dmaengine_terminate_sync() across all error paths in fsl_lpspi_dma_transfer(). Patch 2 fixes a missing RX DMA channel termination when TX descriptor preparation fails. Since the RX channel is already submitted and issued before the TX descriptor is prepared, returning -EINVAL without terminating the RX channel leaves it running against buffers that the SPI core will unmap, potentially causing memory corruption. Link: https://patch.msgid.link/20260525062357.3191349-1-carlos.song@oss.nxp.com
2026-05-26spi: dt-bindings: spi-qpic-snand: Add ipq5210 compatibleVaradarajan Narayanan
Since the QPIC-SPI-NAND flash controller present in ipq5210 is the same as the one found in ipq9574, document the ipq5210 compatible and with ipq9574 as the fallback. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Link: https://patch.msgid.link/20260514-ipq5210-nand-v1-1-cbdd7492e826@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-05-21spi: dt-bindings: fsl-qspi: support SpacemiT K3Zhengyu He
Add the SpacemiT K3 QSPI compatible to the fsl-qspi binding. K3 and K1 use the same QSPI controller, so document the K3 compatible with "spacemit,k1-qspi" as fallback. Signed-off-by: Cody Kang <cody.kang.hk@outlook.com> Signed-off-by: Zhengyu He <hezhy472013@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-1-52bce26e5fd8@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-05-15dt-bindings: Consolidate "sram" property definitionRob Herring (Arm)
The "sram" property has become a de facto standard property, so create a common schema for it and drop all the duplicated definitions. Reviewed-by: Linus Walleij <linusw@kernel.org> Acked-by: Jakub Kicinski <kuba@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Reviewed-by: Liu Ying <victor.liu@nxp.com> #fsl,imx8qxp-dc-command-sequencer.yaml Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> # display/msm Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Tanmay Shah <tanmay.shah@amd.com> Link: https://patch.msgid.link/20260511165942.2774868-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-05-15dt-bindings: Fix phandle-array constraints, againRob Herring (Arm)
The unfortunately named 'phandle-array' property type is really a matrix with phandle and fixed arg cells entries. A matrix property should have 2 levels of items constraints. Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://patch.msgid.link/20260507201749.2605365-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-05-04spi: dt-bindings: add SpacemiT K1 SPI supportAlex Elder
Add support for the SPI controller implemented by the SpacemiT K1 SoC. Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Alex Elder <elder@riscstar.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://patch.msgid.link/20260502-spi-spacemit-k1-v10-1-f412e1ae8a34@riscstar.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-05-04spi: dt-bindings: qcom,spi-qcom-qspi: Add qcom,qcs615-qspi compatibleViken Dadhaniya
Add support for the QSPI controller on QCS615 SoC. Move allOf section after required properties and add if:then constraint to require minimum 2 interconnects for qcs615 variant. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://patch.msgid.link/20260429-spi-nor-v5-1-993016c9711e@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-04-14spi: dt-bindings: fsl: Correct GPIO flags in the exampleKrzysztof Kozlowski
IRQ_TYPE_xxx flags are not correct in the context of GPIO flags. These are simple defines so they could be used in DTS but they will not have the same meaning: IRQ_TYPE_EDGE_RISING = 1 = GPIO_ACTIVE_LOW. Correct the example DTS to use proper flags for chip select GPIOs, assuming the author of the code wanted similar logical behavior: IRQ_TYPE_EDGE_RISING => GPIO_ACTIVE_HIGH Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260413085947.51047-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-04-08Add Renesas RZ/G3L RSPI supportMark Brown
Biju <biju.das.au@gmail.com> says: This patch series adds binding and driver support for RSPI IP found on the RZ/G3L SoC. The RSPI is compatible with RZ/V2H RSPI, but has 2 clocks compared to 3 on RZ/V2H. Link: https://patch.msgid.link/20260408085418.18770-1-biju.das.jz@bp.renesas.com
2026-04-08spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3L SoCBiju Das
Document RSPI IP found on the RZ/G3L SoC. The RSPI IP is compatible with the RZ/V2H RSPI IP, but has 2 clocks compared to 3 on RZ/V2H. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260408085418.18770-2-biju.das.jz@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-18spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC supportTommaso Merciai
Document the RSPI controller on the Renesas RZ/G3E SoC. The block is compatible with the RSPI implementation found on the RZ/V2H(P) family. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/f6b43f0dc64e13b1c9942c164dea30002d4c4466.1771344527.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-18spi: dt-bindings: renesas,rzv2h-rspi: Document dmas propertyTommaso Merciai
Document the dmas property to state it must be specified as TX/RX DMA specifier pairs. This clarifies the expected ordering and improves binding readability without changing behavior. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/ea6ed3b82c5a326732adfc0fcdb2922bfcad2591.1771344527.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-16spi: controller registration fixesMark Brown
Johan Hovold <johan@kernel.org> says: This series fixes a few issues related to controller registration found through inspection.
2026-03-11spi: dt-bindings: sun6i: Allow Dual SPI and Quad SPI for newer SoCsChen-Yu Tsai
Support for Dual SPI and Quad SPI was added to the Linux driver in commit 0605d9fb411f ("spi: sun6i: add quirk for dual and quad SPI modes support") and commit 25453d797d7a ("spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s"). However the binding was never updated to allow these modes. Allow them by adding 2 and 4 to the allowed bus widths for the newer variants. While at it, also add 0 to the allowed bus widths. This signals that RX or TX is not available, i.e. the MISO or MOSI pin is disconnected. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Chen-Yu Tsai <wens@kernel.org> Link: https://patch.msgid.link/20260302153559.3199783-2-wens@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-03spi: dt-bindings: mpfs-spi: remove clock-namesConor Dooley
This binding documented clock-names, but never bothered to document what the name should be, rendering the property useless to software. It's not a required property, so it can just be removed without harming any software that conjured up it's own name for the clock, as they could not rely on it being there to begin with. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260303-spoils-snowbird-99f6e3a2dae3@spud Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-03spi: dt-bindings: mpfs-spi: permit resetsConor Dooley
CoreSPI, CoreQSPI and the hardened versions of them on mpfs and pic64gx have a reset pin. For the first two, usually this is wired to a common fabric reset not managed by software and for the latter two the platform firmware takes them out of reset on first-party boards (or those using modified versions of the vendor firmware), but not all boards may take this approach. Permit providing a reset in devicetree for Linux, or other devicetree-consuming software, to use. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260303-deceiver-rack-82f2b89eac40@spud Signed-off-by: Mark Brown <broonie@kernel.org>
2026-03-02spi: Merge up v7.0-rc2Mark Brown
This gets us a fix for KUnit which allows us to test it.
2026-02-24spi: dt-bindings: snps,dw-abp-ssi: Remove unused bindingsAndy Shevchenko
As stated in the da0a672268b3 ("spi: dw: Remove not-going-to-be-supported code for Baikal SoC") the Baikal platforms are not supported and the respective driver code was removed. Remove the currently unused bindings. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260224115218.3499222-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-02-23spi: dt-bindings: renesas,rzv2h-rspi: allow multiple DMAsCosmin Tanislav
All supported SoCs have multiple DMA controllers that can be used with the RSPI peripheral. The current bindings only allow a single pair of RX and TX DMAs. The DMA core allows specifying multiple DMAs with the same name, and it will pick the first available one. There is an exception in the base dt-schema rules specifically for allowing this behavior (dtschema/schemas/dma/dma.yaml). dma-names: anyOf: - uniqueItems: true - items: # Hack around Renesas bindings which repeat entries to support # multiple possible DMA providers enum: [rx, tx] Allow multiple DMAs to have the same name and only restrict the possible names of the DMA channels, not their count. For RZ/T2H and RZ/N2H SoCs, limit the number of DMA channels to 6, as they have 3 DMA controllers. For RZ/V2H and RZ/V2N SoCs, limit the number of DMA channels to 10, as they have 5 DMA controllers. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-02-05spi: cadence-qspi: Add Renesas RZ/N1 supportMark Brown
Merge series from "Miquel Raynal (Schneider Electric)" <miquel.raynal@bootlin.com>: This series adds support for the QSPI controller available on Renesas RZ/N1S and RZ/N1D SoC. It has been tested with a custom board (see last SPI patch for details), but has been tested by Wolfram (thank you!) on the DB board. Link: https://lore.kernel.org/linux-devicetree/20260116114852.52948-2-wsa+renesas@sang-engineering.com/ Adding support for this SoC required a few adaptations to the Cadence QSPI driver which have already been merged (except one regarding clocks handling). This series contains the remaining patches, the ones actually adding support for the RZ/N1 flavour.
generated by cgit v1.2.3 (git 2.25.1) at 2026-09-10 02:34:46 +0000