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-rw-r--r--include/dt-bindings/reset/cix,sky1-s5-system-control.h163
-rw-r--r--include/dt-bindings/reset/cix,sky1-system-control.h41
-rw-r--r--include/dt-bindings/reset/spacemit,k3-resets.h48
-rw-r--r--include/linux/reset-controller.h21
-rw-r--r--include/linux/reset.h43
5 files changed, 283 insertions, 33 deletions
diff --git a/include/dt-bindings/reset/cix,sky1-s5-system-control.h b/include/dt-bindings/reset/cix,sky1-s5-system-control.h
new file mode 100644
index 000000000000..808bbcbe0c98
--- /dev/null
+++ b/include/dt-bindings/reset/cix,sky1-s5-system-control.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/* Author: Jerry Zhu <jerry.zhu@cixtech.com> */
+#ifndef DT_BINDING_RESET_CIX_SKY1_S5_SYSTEM_CONTROL_H
+#define DT_BINDING_RESET_CIX_SKY1_S5_SYSTEM_CONTROL_H
+
+/* reset for csu_pm */
+#define SKY1_CSU_PM_RESET_N 0
+#define SKY1_SENSORFUSION_RESET_N 1
+#define SKY1_SENSORFUSION_NOC_RESET_N 2
+
+/* reset group0 for s0 domain modules */
+#define SKY1_DDRC_RESET_N 3
+#define SKY1_GIC_RESET_N 4
+#define SKY1_CI700_RESET_N 5
+#define SKY1_SYS_NI700_RESET_N 6
+#define SKY1_MM_NI700_RESET_N 7
+#define SKY1_PCIE_NI700_RESET_N 8
+#define SKY1_GPU_RESET_N 9
+#define SKY1_NPUTOP_RESET_N 10
+#define SKY1_NPUCORE0_RESET_N 11
+#define SKY1_NPUCORE1_RESET_N 12
+#define SKY1_NPUCORE2_RESET_N 13
+#define SKY1_VPU_RESET_N 14
+#define SKY1_ISP_SRESET_N 15
+#define SKY1_ISP_ARESET_N 16
+#define SKY1_ISP_HRESET_N 17
+#define SKY1_ISP_GDCRESET_N 18
+#define SKY1_DPU_RESET0_N 19
+#define SKY1_DPU_RESET1_N 20
+#define SKY1_DPU_RESET2_N 21
+#define SKY1_DPU_RESET3_N 22
+#define SKY1_DPU_RESET4_N 23
+#define SKY1_DP_RESET0_N 24
+#define SKY1_DP_RESET1_N 25
+#define SKY1_DP_RESET2_N 26
+#define SKY1_DP_RESET3_N 27
+#define SKY1_DP_RESET4_N 28
+#define SKY1_DP_PHY_RST_N 29
+
+/* reset group1 for s0 domain modules */
+#define SKY1_AUDIO_HIFI5_RESET_N 30
+#define SKY1_AUDIO_HIFI5_NOC_RESET_N 31
+#define SKY1_CSIDPHY_PRST0_N 32
+#define SKY1_CSIDPHY_CMNRST0_N 33
+#define SKY1_CSI0_RST_N 34
+#define SKY1_CSIDPHY_PRST1_N 35
+#define SKY1_CSIDPHY_CMNRST1_N 36
+#define SKY1_CSI1_RST_N 37
+#define SKY1_CSI2_RST_N 38
+#define SKY1_CSI3_RST_N 39
+#define SKY1_CSIBRDGE0_RST_N 40
+#define SKY1_CSIBRDGE1_RST_N 41
+#define SKY1_CSIBRDGE2_RST_N 42
+#define SKY1_CSIBRDGE3_RST_N 43
+#define SKY1_GMAC0_RST_N 44
+#define SKY1_GMAC1_RST_N 45
+#define SKY1_PCIE0_RESET_N 46
+#define SKY1_PCIE1_RESET_N 47
+#define SKY1_PCIE2_RESET_N 48
+#define SKY1_PCIE3_RESET_N 49
+#define SKY1_PCIE4_RESET_N 50
+
+/* reset group1 for usb phys */
+#define SKY1_USB_DP_PHY0_PRST_N 51
+#define SKY1_USB_DP_PHY1_PRST_N 52
+#define SKY1_USB_DP_PHY2_PRST_N 53
+#define SKY1_USB_DP_PHY3_PRST_N 54
+#define SKY1_USB_DP_PHY0_RST_N 55
+#define SKY1_USB_DP_PHY1_RST_N 56
+#define SKY1_USB_DP_PHY2_RST_N 57
+#define SKY1_USB_DP_PHY3_RST_N 58
+#define SKY1_USBPHY_SS_PST_N 59
+#define SKY1_USBPHY_SS_RST_N 60
+#define SKY1_USBPHY_HS0_PRST_N 61
+#define SKY1_USBPHY_HS1_PRST_N 62
+#define SKY1_USBPHY_HS2_PRST_N 63
+#define SKY1_USBPHY_HS3_PRST_N 64
+#define SKY1_USBPHY_HS4_PRST_N 65
+#define SKY1_USBPHY_HS5_PRST_N 66
+#define SKY1_USBPHY_HS6_PRST_N 67
+#define SKY1_USBPHY_HS7_PRST_N 68
+#define SKY1_USBPHY_HS8_PRST_N 69
+#define SKY1_USBPHY_HS9_PRST_N 70
+
+/* reset group1 for usb controllers */
+#define SKY1_USBC_SS0_PRST_N 71
+#define SKY1_USBC_SS1_PRST_N 72
+#define SKY1_USBC_SS2_PRST_N 73
+#define SKY1_USBC_SS3_PRST_N 74
+#define SKY1_USBC_SS4_PRST_N 75
+#define SKY1_USBC_SS5_PRST_N 76
+#define SKY1_USBC_SS0_RST_N 77
+#define SKY1_USBC_SS1_RST_N 78
+#define SKY1_USBC_SS2_RST_N 79
+#define SKY1_USBC_SS3_RST_N 80
+#define SKY1_USBC_SS4_RST_N 81
+#define SKY1_USBC_SS5_RST_N 82
+#define SKY1_USBC_HS0_PRST_N 83
+#define SKY1_USBC_HS1_PRST_N 84
+#define SKY1_USBC_HS2_PRST_N 85
+#define SKY1_USBC_HS3_PRST_N 86
+#define SKY1_USBC_HS0_RST_N 87
+#define SKY1_USBC_HS1_RST_N 88
+#define SKY1_USBC_HS2_RST_N 89
+#define SKY1_USBC_HS3_RST_N 90
+
+/* reset group0 for rcsu */
+#define SKY1_AUDIO_RCSU_RESET_N 91
+#define SKY1_CI700_RCSU_RESET_N 92
+#define SKY1_CSI_RCSU0_RESET_N 93
+#define SKY1_CSI_RCSU1_RESET_N 94
+#define SKY1_CSU_PM_RCSU_RESET_N 95
+#define SKY1_DDR_BROADCAST_RCSU_RESET_N 96
+#define SKY1_DDR_CTRL_RCSU_0_RESET_N 97
+#define SKY1_DDR_CTRL_RCSU_1_RESET_N 98
+#define SKY1_DDR_CTRL_RCSU_2_RESET_N 99
+#define SKY1_DDR_CTRL_RCSU_3_RESET_N 100
+#define SKY1_DDR_TZC400_RCSU_0_RESET_N 101
+#define SKY1_DDR_TZC400_RCSU_1_RESET_N 102
+#define SKY1_DDR_TZC400_RCSU_2_RESET_N 103
+#define SKY1_DDR_TZC400_RCSU_3_RESET_N 104
+#define SKY1_DP0_RCSU_RESET_N 105
+#define SKY1_DP1_RCSU_RESET_N 106
+#define SKY1_DP2_RCSU_RESET_N 107
+#define SKY1_DP3_RCSU_RESET_N 108
+#define SKY1_DP4_RCSU_RESET_N 109
+#define SKY1_DPU0_RCSU_RESET_N 110
+#define SKY1_DPU1_RCSU_RESET_N 111
+#define SKY1_DPU2_RCSU_RESET_N 112
+#define SKY1_DPU3_RCSU_RESET_N 113
+#define SKY1_DPU4_RCSU_RESET_N 114
+#define SKY1_DSU_RCSU_RESET_N 115
+#define SKY1_FCH_RCSU_RESET_N 116
+#define SKY1_GICD_RCSU_RESET_N 117
+#define SKY1_GMAC_RCSU_RESET_N 118
+#define SKY1_GPU_RCSU_RESET_N 119
+#define SKY1_ISP_RCSU0_RESET_N 120
+#define SKY1_ISP_RCSU1_RESET_N 121
+#define SKY1_NI700_MMHUB_RCSU_RESET_N 122
+
+/* reset group1 for rcsu */
+#define SKY1_NPU_RCSU_RESET_N 123
+#define SKY1_NI700_PCIE_RCSU_RESET_N 124
+#define SKY1_PCIE_X421_RCSU_RESET_N 125
+#define SKY1_PCIE_X8_RCSU_RESET_N 126
+#define SKY1_SF_RCSU_RESET_N 127
+#define SKY1_RCSU_SMMU_MMHUB_RESET_N 128
+#define SKY1_RCSU_SMMU_PCIEHUB_RESET_N 129
+#define SKY1_RCSU_SYSHUB_RESET_N 130
+#define SKY1_NI700_SMN_RCSU_RESET_N 131
+#define SKY1_NI700_SYSHUB_RCSU_RESET_N 132
+#define SKY1_RCSU_USB2_HOST0_RESET_N 133
+#define SKY1_RCSU_USB2_HOST1_RESET_N 134
+#define SKY1_RCSU_USB2_HOST2_RESET_N 135
+#define SKY1_RCSU_USB2_HOST3_RESET_N 136
+#define SKY1_RCSU_USB3_TYPEA_DRD_RESET_N 137
+#define SKY1_RCSU_USB3_TYPEC_DRD_RESET_N 138
+#define SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N 139
+#define SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N 140
+#define SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N 141
+#define SKY1_VPU_RCSU_RESET_N 142
+
+#endif
diff --git a/include/dt-bindings/reset/cix,sky1-system-control.h b/include/dt-bindings/reset/cix,sky1-system-control.h
new file mode 100644
index 000000000000..7a16fc4ef3b5
--- /dev/null
+++ b/include/dt-bindings/reset/cix,sky1-system-control.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/* Author: Jerry Zhu <jerry.zhu@cixtech.com> */
+#ifndef DT_BINDING_RESET_CIX_SKY1_SYSTEM_CONTROL_H
+#define DT_BINDING_RESET_CIX_SKY1_SYSTEM_CONTROL_H
+
+/* func reset for sky1 fch */
+#define SW_I3C0_RST_FUNC_G_N 0
+#define SW_I3C0_RST_FUNC_I_N 1
+#define SW_I3C1_RST_FUNC_G_N 2
+#define SW_I3C1_RST_FUNC_I_N 3
+#define SW_UART0_RST_FUNC_N 4
+#define SW_UART1_RST_FUNC_N 5
+#define SW_UART2_RST_FUNC_N 6
+#define SW_UART3_RST_FUNC_N 7
+#define SW_TIMER_RST_FUNC_N 8
+
+/* apb reset for sky1 fch */
+#define SW_I3C0_RST_APB_N 9
+#define SW_I3C1_RST_APB_N 10
+#define SW_DMA_RST_AXI_N 11
+#define SW_UART0_RST_APB_N 12
+#define SW_UART1_RST_APB_N 13
+#define SW_UART2_RST_APB_N 14
+#define SW_UART3_RST_APB_N 15
+#define SW_SPI0_RST_APB_N 16
+#define SW_SPI1_RST_APB_N 17
+#define SW_I2C0_RST_APB_N 18
+#define SW_I2C1_RST_APB_N 19
+#define SW_I2C2_RST_APB_N 20
+#define SW_I2C3_RST_APB_N 21
+#define SW_I2C4_RST_APB_N 22
+#define SW_I2C5_RST_APB_N 23
+#define SW_I2C6_RST_APB_N 24
+#define SW_I2C7_RST_APB_N 25
+#define SW_GPIO_RST_APB_N 26
+
+/* fch rst for xspi */
+#define SW_XSPI_REG_RST_N 27
+#define SW_XSPI_SYS_RST_N 28
+
+#endif
diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
index 79ac1c22b7b5..dc1ef009ba79 100644
--- a/include/dt-bindings/reset/spacemit,k3-resets.h
+++ b/include/dt-bindings/reset/spacemit,k3-resets.h
@@ -97,11 +97,11 @@
#define RESET_APMU_SDH0 13
#define RESET_APMU_SDH1 14
#define RESET_APMU_SDH2 15
-#define RESET_APMU_USB2 16
-#define RESET_APMU_USB3_PORTA 17
-#define RESET_APMU_USB3_PORTB 18
-#define RESET_APMU_USB3_PORTC 19
-#define RESET_APMU_USB3_PORTD 20
+#define RESET_APMU_USB2_AHB 16
+#define RESET_APMU_USB2_VCC 17
+#define RESET_APMU_USB2_PHY 18
+#define RESET_APMU_USB3_A_AHB 19
+#define RESET_APMU_USB3_A_VCC 20
#define RESET_APMU_QSPI 21
#define RESET_APMU_QSPI_BUS 22
#define RESET_APMU_DMA 23
@@ -132,8 +132,8 @@
#define RESET_APMU_CPU7_SW 48
#define RESET_APMU_C1_MPSUB_SW 49
#define RESET_APMU_MPSUB_DBG 50
-#define RESET_APMU_UCIE 51
-#define RESET_APMU_RCPU 52
+#define RESET_APMU_USB3_A_PHY 51 /* USB3 A */
+#define RESET_APMU_USB3_B_AHB 52
#define RESET_APMU_DSI4LN2_ESCCLK 53
#define RESET_APMU_DSI4LN2_LCD_SW 54
#define RESET_APMU_DSI4LN2_LCD_MCLK 55
@@ -143,16 +143,40 @@
#define RESET_APMU_UFS_ACLK 59
#define RESET_APMU_EDP0 60
#define RESET_APMU_EDP1 61
-#define RESET_APMU_PCIE_PORTA 62
-#define RESET_APMU_PCIE_PORTB 63
-#define RESET_APMU_PCIE_PORTC 64
-#define RESET_APMU_PCIE_PORTD 65
-#define RESET_APMU_PCIE_PORTE 66
+#define RESET_APMU_USB3_B_VCC 62 /* USB3 B */
+#define RESET_APMU_USB3_B_PHY 63
+#define RESET_APMU_USB3_C_AHB 64
+#define RESET_APMU_USB3_C_VCC 65
+#define RESET_APMU_USB3_C_PHY 66
#define RESET_APMU_EMAC0 67
#define RESET_APMU_EMAC1 68
#define RESET_APMU_EMAC2 69
#define RESET_APMU_ESPI_MCLK 70
#define RESET_APMU_ESPI_SCLK 71
+#define RESET_APMU_USB3_D_AHB 72 /* USB3 D */
+#define RESET_APMU_USB3_D_VCC 73
+#define RESET_APMU_USB3_D_PHY 74
+#define RESET_APMU_UCIE_IP 75
+#define RESET_APMU_UCIE_HOT 76
+#define RESET_APMU_UCIE_MON 77
+#define RESET_APMU_RCPU_AUDIO_SYS 78
+#define RESET_APMU_RCPU_MCU_CORE 79
+#define RESET_APMU_RCPU_AUDIO_APMU 80
+#define RESET_APMU_PCIE_A_DBI 81
+#define RESET_APMU_PCIE_A_SLAVE 82
+#define RESET_APMU_PCIE_A_MASTER 83
+#define RESET_APMU_PCIE_B_DBI 84
+#define RESET_APMU_PCIE_B_SLAVE 85
+#define RESET_APMU_PCIE_B_MASTER 86
+#define RESET_APMU_PCIE_C_DBI 87
+#define RESET_APMU_PCIE_C_SLAVE 88
+#define RESET_APMU_PCIE_C_MASTER 89
+#define RESET_APMU_PCIE_D_DBI 90
+#define RESET_APMU_PCIE_D_SLAVE 91
+#define RESET_APMU_PCIE_D_MASTER 92
+#define RESET_APMU_PCIE_E_DBI 93
+#define RESET_APMU_PCIE_E_SLAVE 94
+#define RESET_APMU_PCIE_E_MASTER 95
/* DCIU resets*/
#define RESET_DCIU_HDMA 0
diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h
index 46514cb1b9e0..52a5a4e81f18 100644
--- a/include/linux/reset-controller.h
+++ b/include/linux/reset-controller.h
@@ -3,7 +3,10 @@
#define _LINUX_RESET_CONTROLLER_H_
#include <linux/list.h>
+#include <linux/mutex.h>
+struct fwnode_handle;
+struct fwnode_reference_args;
struct reset_controller_dev;
/**
@@ -35,14 +38,16 @@ struct of_phandle_args;
* @reset_control_head: head of internal list of requested reset controls
* @dev: corresponding driver model device struct
* @of_node: corresponding device tree node as phandle target
- * @of_args: for reset-gpios controllers: corresponding phandle args with
- * of_node and GPIO number complementing of_node; either this or
- * of_node should be present
* @of_reset_n_cells: number of cells in reset line specifiers
* @of_xlate: translation function to translate from specifier as found in the
- * device tree to id as given to the reset control ops, defaults
- * to :c:func:`of_reset_simple_xlate`.
+ * device tree to id as given to the reset control ops
+ * @fwnode: firmware node associated with this device
+ * @fwnode_reset_n_cells: number of cells in reset line specifiers
+ * @fwnode_xlate: translation function to translate from firmware specifier to
+ * id as given to the reset control ops, defaults to
+ * :c:func:`fwnode_reset_simple_xlate`
* @nr_resets: number of reset controls in this reset controller device
+ * @lock: protects the reset control list from concurrent access
*/
struct reset_controller_dev {
const struct reset_control_ops *ops;
@@ -51,11 +56,15 @@ struct reset_controller_dev {
struct list_head reset_control_head;
struct device *dev;
struct device_node *of_node;
- const struct of_phandle_args *of_args;
int of_reset_n_cells;
int (*of_xlate)(struct reset_controller_dev *rcdev,
const struct of_phandle_args *reset_spec);
+ struct fwnode_handle *fwnode;
+ int fwnode_reset_n_cells;
+ int (*fwnode_xlate)(struct reset_controller_dev *rcdev,
+ const struct fwnode_reference_args *reset_spec);
unsigned int nr_resets;
+ struct mutex lock;
};
#if IS_ENABLED(CONFIG_RESET_CONTROLLER)
diff --git a/include/linux/reset.h b/include/linux/reset.h
index 44f9e3415f92..9c391cf0c822 100644
--- a/include/linux/reset.h
+++ b/include/linux/reset.h
@@ -5,10 +5,12 @@
#include <linux/bits.h>
#include <linux/err.h>
#include <linux/errno.h>
+#include <linux/of.h>
#include <linux/types.h>
struct device;
struct device_node;
+struct fwnode_handle;
struct reset_control;
/**
@@ -84,7 +86,7 @@ int reset_control_bulk_deassert(int num_rstcs, struct reset_control_bulk_data *r
int reset_control_bulk_acquire(int num_rstcs, struct reset_control_bulk_data *rstcs);
void reset_control_bulk_release(int num_rstcs, struct reset_control_bulk_data *rstcs);
-struct reset_control *__of_reset_control_get(struct device_node *node,
+struct reset_control *__fwnode_reset_control_get(struct fwnode_handle *fwnode,
const char *id, int index, enum reset_control_flags flags);
struct reset_control *__reset_control_get(struct device *dev, const char *id,
int index, enum reset_control_flags flags);
@@ -103,7 +105,8 @@ int __devm_reset_control_bulk_get(struct device *dev, int num_rstcs,
struct reset_control *devm_reset_control_array_get(struct device *dev,
enum reset_control_flags flags);
-struct reset_control *of_reset_control_array_get(struct device_node *np, enum reset_control_flags);
+struct reset_control *fwnode_reset_control_array_get(struct fwnode_handle *fwnode,
+ enum reset_control_flags);
int reset_control_get_count(struct device *dev);
@@ -152,8 +155,8 @@ static inline int __device_reset(struct device *dev, bool optional)
return optional ? 0 : -ENOTSUPP;
}
-static inline struct reset_control *__of_reset_control_get(
- struct device_node *node,
+static inline struct reset_control *__fwnode_reset_control_get(
+ struct fwnode_handle *fwnode,
const char *id, int index, enum reset_control_flags flags)
{
bool optional = flags & RESET_CONTROL_FLAGS_BIT_OPTIONAL;
@@ -242,7 +245,7 @@ devm_reset_control_array_get(struct device *dev, enum reset_control_flags flags)
}
static inline struct reset_control *
-of_reset_control_array_get(struct device_node *np, enum reset_control_flags flags)
+fwnode_reset_control_array_get(struct fwnode_handle *fwnode, enum reset_control_flags flags)
{
bool optional = flags & RESET_CONTROL_FLAGS_BIT_OPTIONAL;
@@ -500,7 +503,8 @@ reset_control_bulk_get_optional_shared(struct device *dev, int num_rstcs,
static inline struct reset_control *of_reset_control_get_exclusive(
struct device_node *node, const char *id)
{
- return __of_reset_control_get(node, id, 0, RESET_CONTROL_EXCLUSIVE);
+ return __fwnode_reset_control_get(of_fwnode_handle(node), id, 0,
+ RESET_CONTROL_EXCLUSIVE);
}
/**
@@ -520,7 +524,8 @@ static inline struct reset_control *of_reset_control_get_exclusive(
static inline struct reset_control *of_reset_control_get_optional_exclusive(
struct device_node *node, const char *id)
{
- return __of_reset_control_get(node, id, 0, RESET_CONTROL_OPTIONAL_EXCLUSIVE);
+ return __fwnode_reset_control_get(of_fwnode_handle(node), id, 0,
+ RESET_CONTROL_OPTIONAL_EXCLUSIVE);
}
/**
@@ -545,7 +550,8 @@ static inline struct reset_control *of_reset_control_get_optional_exclusive(
static inline struct reset_control *of_reset_control_get_shared(
struct device_node *node, const char *id)
{
- return __of_reset_control_get(node, id, 0, RESET_CONTROL_SHARED);
+ return __fwnode_reset_control_get(of_fwnode_handle(node), id, 0,
+ RESET_CONTROL_SHARED);
}
/**
@@ -562,7 +568,8 @@ static inline struct reset_control *of_reset_control_get_shared(
static inline struct reset_control *of_reset_control_get_exclusive_by_index(
struct device_node *node, int index)
{
- return __of_reset_control_get(node, NULL, index, RESET_CONTROL_EXCLUSIVE);
+ return __fwnode_reset_control_get(of_fwnode_handle(node), NULL, index,
+ RESET_CONTROL_EXCLUSIVE);
}
/**
@@ -590,7 +597,8 @@ static inline struct reset_control *of_reset_control_get_exclusive_by_index(
static inline struct reset_control *of_reset_control_get_shared_by_index(
struct device_node *node, int index)
{
- return __of_reset_control_get(node, NULL, index, RESET_CONTROL_SHARED);
+ return __fwnode_reset_control_get(of_fwnode_handle(node), NULL, index,
+ RESET_CONTROL_SHARED);
}
/**
@@ -1032,30 +1040,35 @@ devm_reset_control_array_get_optional_shared(struct device *dev)
static inline struct reset_control *
of_reset_control_array_get_exclusive(struct device_node *node)
{
- return of_reset_control_array_get(node, RESET_CONTROL_EXCLUSIVE);
+ return fwnode_reset_control_array_get(of_fwnode_handle(node),
+ RESET_CONTROL_EXCLUSIVE);
}
static inline struct reset_control *
of_reset_control_array_get_exclusive_released(struct device_node *node)
{
- return of_reset_control_array_get(node, RESET_CONTROL_EXCLUSIVE_RELEASED);
+ return fwnode_reset_control_array_get(of_fwnode_handle(node),
+ RESET_CONTROL_EXCLUSIVE_RELEASED);
}
static inline struct reset_control *
of_reset_control_array_get_shared(struct device_node *node)
{
- return of_reset_control_array_get(node, RESET_CONTROL_SHARED);
+ return fwnode_reset_control_array_get(of_fwnode_handle(node),
+ RESET_CONTROL_SHARED);
}
static inline struct reset_control *
of_reset_control_array_get_optional_exclusive(struct device_node *node)
{
- return of_reset_control_array_get(node, RESET_CONTROL_OPTIONAL_EXCLUSIVE);
+ return fwnode_reset_control_array_get(of_fwnode_handle(node),
+ RESET_CONTROL_OPTIONAL_EXCLUSIVE);
}
static inline struct reset_control *
of_reset_control_array_get_optional_shared(struct device_node *node)
{
- return of_reset_control_array_get(node, RESET_CONTROL_OPTIONAL_SHARED);
+ return fwnode_reset_control_array_get(of_fwnode_handle(node),
+ RESET_CONTROL_OPTIONAL_SHARED);
}
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-20 05:38:39 +0000