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-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gpu.c13
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_gpu.c4
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_gpu.h1
3 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index ae592022bebc..615509c8917e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2604,6 +2604,17 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
return 0;
}
+static bool a6xx_aqe_is_enabled(struct adreno_gpu *adreno_gpu)
+{
+ struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+
+ /*
+ * AQE uses preemption context record as scratch pad, so check if
+ * preemption is enabled
+ */
+ return (adreno_gpu->base.nr_rings > 1) && !!a6xx_gpu->aqe_bo;
+}
+
static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
{
struct msm_drm_private *priv = dev->dev_private;
@@ -2803,6 +2814,7 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = {
.bus_halt = a6xx_bus_clear_pending_transactions,
.mmu_fault_handler = a6xx_fault_handler,
.gx_is_on = a7xx_gmu_gx_is_on,
+ .aqe_is_enabled = a6xx_aqe_is_enabled,
};
const struct adreno_gpu_funcs a8xx_gpu_funcs = {
@@ -2831,4 +2843,5 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = {
.bus_halt = a8xx_bus_clear_pending_transactions,
.mmu_fault_handler = a8xx_fault_handler,
.gx_is_on = a8xx_gmu_gx_is_on,
+ .aqe_is_enabled = a6xx_aqe_is_enabled,
};
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 0dbeb332f8d1..85d135a9d336 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -441,6 +441,10 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
case MSM_PARAM_HAS_PRR:
*value = adreno_smmu_has_prr(gpu);
return 0;
+ case MSM_PARAM_AQE:
+ *value = !!(adreno_gpu->funcs->aqe_is_enabled &&
+ adreno_gpu->funcs->aqe_is_enabled(adreno_gpu));
+ return 0;
default:
return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param);
}
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 834f6fd2a89e..ec643b84646b 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -80,6 +80,7 @@ struct adreno_gpu_funcs {
void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off);
int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data);
bool (*gx_is_on)(struct adreno_gpu *adreno_gpu);
+ bool (*aqe_is_enabled)(struct adreno_gpu *adreno_gpu);
};
struct adreno_reglist {