diff options
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_bw.c | 39 |
1 files changed, 26 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 26b294544d10..d7b2bc80f8e3 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -482,6 +482,28 @@ static const struct intel_display_bw_params xelpdp_bw_params = { .displayrtids = 256, }; +static const struct intel_display_bw_params *get_display_bw_params(struct intel_display *display) +{ + if (DISPLAY_VER(display) >= 14) { + return &xelpdp_bw_params; + } else if (DISPLAY_VER(display) >= 12) { + /* + * RKL's SoC was based on ICL and the display, even though being + * gen12, had changes to the memory interface to match gen11's, + * consequently inheriting gen11's display-specific bandwidth + * parameters. + */ + if (display->platform.rocketlake) + return &gen11_bw_params; + else + return &gen12_bw_params; + } else if (DISPLAY_VER(display) == 11) { + return &gen11_bw_params; + } + + return NULL; +} + static int icl_get_bw_info(struct intel_display *display, const struct dram_info *dram_info, const struct intel_soc_bw_params *soc_bw_params, @@ -832,12 +854,14 @@ void intel_bw_init_hw(struct intel_display *display) { const struct dram_info *dram_info; const struct intel_soc_bw_params *soc_bw_params; + const struct intel_display_bw_params *display_bw_params; if (!HAS_DISPLAY(display)) return; dram_info = intel_dram_info(display); soc_bw_params = get_soc_bw_params(display, dram_info); + display_bw_params = get_display_bw_params(display); /* * Starting with Xe3p_LPD, the hardware tells us whether memory has ECC @@ -850,23 +874,12 @@ void intel_bw_init_hw(struct intel_display *display) if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) { xe2_hpd_get_bw_info(display, dram_info, soc_bw_params); - } else if (DISPLAY_VER(display) >= 14) { - tgl_get_bw_info(display, dram_info, soc_bw_params, &xelpdp_bw_params); } else if (display->platform.dg2) { dg2_get_bw_info(display); } else if (DISPLAY_VER(display) >= 12) { - /* - * RKL's SoC was based on ICL and the display, even though being - * gen12, had changes to the memory interface to match gen11's, - * consequently inheriting gen11's display-specific bandwidth - * parameters. - */ - if (display->platform.rocketlake) - tgl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params); - else - tgl_get_bw_info(display, dram_info, soc_bw_params, &gen12_bw_params); + tgl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params); } else if (DISPLAY_VER(display) == 11) { - icl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params); + icl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params); } } |