drm/i915/dsb: shift delayed-vblank DSL wait start by one scanline

In intel_dsb_wait_for_delayed_vblank() the VRR path issues a
WAIT_DSL_OUT(safe_window_start, vmin_safe_window_end) followed by a
WAIT_USEC for SCL+1 scanlines to land on the delayed vblank.

Experimentally, DSB appears to observe a slightly stale PIPEDSL value.
When the actual scanline has just reached safe_window_start, the DSB
may still see a value at or before that boundary when WAIT_DSL_OUT is
evaluated, causing the wait to complete immediately.

As a result, the subsequent WAIT_USEC executes too early, and the
flip-done interrupt fires roughly one frame ahead of the delayed vblank.

Shift the scanline start back by one to ensure the wait window is
entered reliably.

v2: Replace explicit one-scanline delay with scanline boundary
    adjustment (safe_window_start - 1). (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260608123711.1121908-2-ankit.k.nautiyal@intel.com

0 files changed, 0 insertions, 0 deletions