diff options
| author | Peter Ujfalusi <peter.ujfalusi@linux.intel.com> | 2026-08-05 11:24:12 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-08-05 13:34:35 +0100 |
| commit | f39a68ed08bb6eef0ae711b41d645ee5e9448c09 (patch) | |
| tree | d3e628532bb8403f4614d2d8179dd145988f4eb2 /tools/perf/scripts/python | |
| parent | d74aac116cfb2058b15df53996d23232b310f7ff (diff) | |
ASoC: cs35l45: sort the register default table
reg_defaults must be sorted by ascending register address, as
regcache_lookup_reg() locates entries in it with bsearch(). See commit
fd80df352ba1 ("regcache: Add support for sorting defaults arrays").
cs35l45_defaults[] lists the DSP1_RX*_RATE and DSP1_TX*_RATE registers
(0x02b80080 - 0x02b802b8) in the middle of the table, ahead of entries with
much lower addresses, so the binary search does not find 36 of its 73
entries. regcache_reg_needs_sync() then cannot compare those against their
default and reports that a sync is needed, so they are written to the
device on every regcache_sync() even when they were never touched.
Sort the table by register address.
Fixes: 74b14e2850a3 ("ASoC: cs35l45: DSP Support")
Cc: stable@vger.kernel.org
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Reviewed-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://patch.msgid.link/20260805082413.26174-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions
