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| author | Jakub Kicinski <kuba@kernel.org> | 2026-08-18 09:41:02 -0700 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2026-08-18 09:41:02 -0700 |
| commit | de9c18ad3f3a20732aa3b5e8655fe78fa1527dc5 (patch) | |
| tree | 2e67021b3762b5a41213e65df0f79e9660fa6a63 /tools/perf/scripts/python | |
| parent | 25b00c01fe1062ef1f2aaa3c4ee6638ec9beb239 (diff) | |
| parent | 1db73ce01856c983bcc7789c4dffc6b5b8f41a23 (diff) | |
Merge branch 'dpll-zl3073x-add-ptp-clock-support'
Ivan Vecera says:
====================
dpll: zl3073x: add PTP clock support
Add PTP hardware clock support to the zl3073x DPLL driver.
Patch 1 scales the poll sleep interval in zl3073x_poll_zero_u8()
proportionally to the timeout to avoid excessive bus traffic for
the longer PTP-related timeouts.
Patch 2 adds low-level channel operations for ToD read/write/adjust,
output phase step, delta frequency offset write and TIE write as
building blocks for PTP callbacks.
Patch 3 registers a PTP clock device for each DPLL channel with
gettimex64, settime64, adjtime, adjfine, adjphase and getmaxphase
callbacks. Callback availability adapts to the current channel
state - adjfine requires NCO pin connected, adjphase uses TIE write
when tracking a reference, and adjtime selects the appropriate
mechanism automatically. Periodic output support will be added in a
follow-up series.
====================
Link: https://patch.msgid.link/20260814082656.306534-1-ivecera@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions
