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| author | Vasant Hegde <vasant.hegde@amd.com> | 2026-08-11 05:22:57 +0000 |
|---|---|---|
| committer | Joerg Roedel <joerg.roedel@amd.com> | 2026-08-11 09:03:57 +0200 |
| commit | cb2860ad6c4ff7e15bb69c7e3a6842bbea743229 (patch) | |
| tree | 55a99fee2276febbb6008658c5c29928b0dd4b81 /tools/perf/scripts/python | |
| parent | c94252cd5bbcdab3b1a9a25c638302678fa7721f (diff) | |
iommu/amd: Add SNP page mode 0 support
Newer AMD IOMMUs supports DTE[Mode]=0 for SNP-enabled system. This is
detected using new feature bit (EFR2[SNP_Page_Mode_0_Sup]). If this
feature is enabled, then IOMMU supports:
- Passthrough mode (i.e. iommu=pt)
- amd_iommu=pgtbl_v2: Forcing Linux DMA-API to use IOMMU v2 page table
- Setting up device for SVA mode in the host.
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Tested-by: Amandeep Kaur Longia <AmandeepKaur.Longia@amd.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions