diff options
| author | Sascha Bischoff <Sascha.Bischoff@arm.com> | 2026-03-19 15:53:05 +0000 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2026-03-19 18:21:27 +0000 |
| commit | 9d6d9514c08f462d162040b48526bda60def9de1 (patch) | |
| tree | 7cb16329882bd96b19bcd19c512d8096316950c1 /tools/perf/scripts/python | |
| parent | a258a383b91774ac646517ec1003a442964d8946 (diff) | |
KVM: arm64: gic-v5: Support GICv5 FGTs & FGUs
Extend the existing FGT/FGU infrastructure to include the GICv5 trap
registers (ICH_HFGRTR_EL2, ICH_HFGWTR_EL2, ICH_HFGITR_EL2). This
involves mapping the trap registers and their bits to the
corresponding feature that introduces them (FEAT_GCIE for all, in this
case), and mapping each trap bit to the system register/instruction
controlled by it.
As of this change, none of the GICv5 instructions or register accesses
are being trapped.
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260319154937.3619520-14-sascha.bischoff@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions