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| author | Maher Sanalla <msanalla@nvidia.com> | 2022-11-28 18:00:17 +0200 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@nvidia.com> | 2023-01-10 21:24:39 -0800 |
| commit | 8d231dbc3b10155727bcfa9e543d397ad357f14f (patch) | |
| tree | d5ce74c6795a57eab9510deb6cdd68f0e66c2bc1 /tools/perf/scripts/python | |
| parent | a6f536063b69102adf3588fbc0bb4f08d6c8cb82 (diff) | |
net/mlx5: Expose shared buffer registers bits and structs
Add the shared receive buffer management and configuration registers:
1. SBPR - Shared Buffer Pools Register
2. SBCM - Shared Buffer Class Management Register
Signed-off-by: Maher Sanalla <msanalla@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions