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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-03-25 19:24:28 +0000 |
|---|---|---|
| committer | Thomas Gleixner <tglx@kernel.org> | 2026-03-26 16:56:23 +0100 |
| commit | 87404cb8cae43b680caaaa621280e71969a09147 (patch) | |
| tree | 771ce9020c9066661ca64c2132816af7a5c2b768 /tools/perf/scripts/python | |
| parent | 2f814778950ecc99ca5e71472b626dddb2d2b756 (diff) | |
irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro
The IRQC_TINT_START value is different for RZ/G3L and RZ/G2L SoC. Add
tint_start variable in struct rzg2l_hw_info to handle this difference and
drop the macro IRQC_TINT_START.
While at it, update the variable type of titseln, tssr_offset, tssr_index,
index, and sense to unsigned int, in rzg2l_tint_set_edge() as these
variables are used only for calculation.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260325192451.172562-14-biju.das.jz@bp.renesas.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions