dt-bindings: clock: versal-clk: Fix Versal NET clock validation

The Versal NET clock controller compatible is specified as:
  compatible = "xlnx,versal-net-clk", "xlnx,versal-clk";

with xlnx,versal-clk listed as fallback. The original binding had
two separate if/then blocks - one matching xlnx,versal-clk (2 clocks)
and another matching xlnx,versal-net-clk (3 clocks). Since both
compatible strings are present, both conditions matched simultaneously
and JSON Schema applied the more restrictive 2-clock constraint,
causing false "too long" validation errors for Versal NET.

Define clock-names at the top-level and use if/then only to constrain
the clock count (2 for Versal, 3 for Versal NET). Add a dedicated
example for the Versal NET 3-clock configuration.

Fixes: 39118392d19a ("dt-bindings: Remove alt_ref from versal")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/202e448e57cf979e1b5be61da0bad7778defdd4e.1783516336.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

0 files changed, 0 insertions, 0 deletions