clk: renesas: r9a09g047: Add audio clock and reset support

Add clock and reset entries for audio-related modules on the RZ/G3E SoC.

Target modules are:
 - SSIU (Serial Sound Interface Unit) with SSI ch0-ch9,
 - SCU (Sampling Rate Converter Unit) with SRC ch0-ch9, DVC ch0-ch1,
   CTU/MIX ch0-ch1,
 - DMACpp (Audio DMA Controller),
 - ADG (Audio Clock Generator) with divider input clocks and audio
   master clock outputs.

The ADG SSI clock outputs (adg_ssi[0-9]_clk) are parented on
CLK_PLLCLN_DIV8 as a deliberate simplification: the ADG dynamically
muxes each output between adg_0_clk_195m and audio_clk[a,b,c] at
runtime via ADG_AUDIO_CLK_SEL{0,1,2}, owned by the rsnd-adg driver.

While at it, reorder plldty_div16 to group it with the other plldty
fixed dividers.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260525110603.4018170-3-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

0 files changed, 0 insertions, 0 deletions