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| author | Ryan Chen <ryan_chen@aspeedtech.com> | 2026-06-24 13:45:00 +0800 |
|---|---|---|
| committer | Brian Masney <bmasney@redhat.com> | 2026-07-28 11:25:30 -0400 |
| commit | 5ffa9d308c7a30192f1b05ee0bfd9e1976493a54 (patch) | |
| tree | 314c0dd41c75dc9babc3efe9c1b0a1ec172b28bb /tools/perf/scripts/python | |
| parent | 51be18310cd82fc4f1692d9cb7c4f53d26cacd74 (diff) | |
clk: aspeed: add AST2700 PECI clock
Register the SoC1 PECI clock as a mux selected by SCU1_CLK_SEL2 bit 16,
choosing between the 25MHz CLKIN and HPLL/4. Add the HPLL/4 fixed factor
clock to serve as the second mux parent.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions