diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2026-02-28 16:09:25 +0800 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2026-03-26 22:17:00 +0530 |
| commit | 5f73cf1db829c21b7fd44a8d2587cd395b1b2d76 (patch) | |
| tree | 0d2bb84c018d5a030ef73e42e9788816cec6125b /tools/perf/scripts/python | |
| parent | 3b55079d6387805ede687e234d84669aeb0f7e98 (diff) | |
PCI: imx6: Skip waiting for L2/L3 Ready on i.MX6SX
On i.MX6SX, the LTSSM registers become inaccessible after the
PME_Turn_Off message is sent to the link. So there is no way to verify
whether the link has entered L2/L3 Ready state or not.
Hence, set IMX_PCIE_FLAG_SKIP_L23_READY flag for i.MX6SX SoC to skip the
L2/L3 Ready state polling and let the DWC core wait for 10ms after sending
the PME_Turn_Off message as per the PCIe spec r6.0, sec 5.3.3.2.1.
Fixes: a528d1a72597 ("PCI: imx6: Use DWC common suspend resume method")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[mani: commit log]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260228080925.1558395-1-hongxing.zhu@nxp.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions