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| author | Ashish Mhetre <amhetre@nvidia.com> | 2026-06-22 06:54:10 +0000 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2026-07-31 17:38:20 +0200 |
| commit | 5af7a8a522f61ae2a3e5038c889e231e56d63526 (patch) | |
| tree | 3e000468e86c2202ac45cc57a7f3f89b314a43c7 /tools/perf/scripts/python | |
| parent | 96c5696a58fa527873c261f74d74f81303e756fe (diff) | |
arm64: tegra: Fix CMDQV interrupt type on Tegra264
The CMDQV interrupts on Tegra264 are described as level-triggered, but
per the hardware interrupt documentation these interrupts are actually
edge-triggered.
Correct the interrupt type for all CMDQV nodes from IRQ_TYPE_LEVEL_HIGH
to IRQ_TYPE_EDGE_RISING.
Fixes: fe57d0ac4835 ("arm64: tegra: Add nodes for CMDQV")
Reported-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions