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| author | Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> | 2026-06-11 19:00:44 +0000 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-06-28 20:02:15 -0500 |
| commit | 52c7084c8fe57c259e50ff0a7d4f99ccecfc4c7a (patch) | |
| tree | 64377bbb1d2be932e202a1c55776b6dfc4de2b82 /tools/perf/scripts/python | |
| parent | dc59e4fea9d83f03bad6bddf3fa2e52491777482 (diff) | |
arm64: dts: qcom: glymur: fix PCIe SMMU interrupts
The PCIe SMMUv3 wired interrupts are routed to GIC extended SPI INTIDs
4100, 4098 and 4096. Describe them as ESPIs with the ESPI-relative
interrupt numbers instead of regular SPIs 964, 962 and 960.
Assisted-by: Codex:GPT-5.5
Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi")
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260611-glymur-pcie-smmu-espi-v1-1-5effbaa3e1af@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions