diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-09-11 18:18:36 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-09-18 23:25:18 +0300 |
| commit | 52c4abeec6fd40f492dead85beb2652719f479c3 (patch) | |
| tree | 61ab2af72b7aac0fd7708854af9d42cdb0c28bfc /tools/perf/scripts/python | |
| parent | 2478e2234d7d0196138fa2be3e5e538eae3ff888 (diff) | |
drm/i915/psr: Fix PSR sink enable sequence
According to the eDP spec, the source must first configure all
PSR related DPCD registers apart from the actual enable bit,
and only then set the enable bit. Split the current single DPCD
write to two to match the spec.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240911151836.16800-1-ville.syrjala@linux.intel.com
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions