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| author | Chen-Yu Tsai <wenst@chromium.org> | 2026-07-28 17:17:59 +0800 |
|---|---|---|
| committer | Brian Masney <bmasney@redhat.com> | 2026-07-28 11:25:30 -0400 |
| commit | 442d24ce7f4c09a7d14b949d7a6b640bd63cc4e0 (patch) | |
| tree | f5b381567735717cafca516cb9d03af3f137a9fe /tools/perf/scripts/python | |
| parent | 3ed463b69be8120d8f674051f0fe3304ef9839cc (diff) | |
dt-bindings: clock: mediatek: Add mt8173 mfgtop
The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
in the datasheet, that contains clock gates, some power sequence signal
delays, and other unknown registers that get toggled when the GPU is
powered on.
The clock gates are exposed as clocks provided by a clock controller,
while the power sequencing bits are exposed as one singular power domain.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Brian Masney <bmasney@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions