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| author | Thomas Zimmermann <tzimmermann@suse.de> | 2026-03-27 14:33:04 +0100 |
|---|---|---|
| committer | Thomas Zimmermann <tzimmermann@suse.de> | 2026-04-08 11:04:49 +0200 |
| commit | 24946c2aa0f1bbafe8089187aa08fb5d417fd069 (patch) | |
| tree | a4ad0c66ed6736e843179c814230dfe6f4f9943e /tools/perf/scripts/python | |
| parent | fe727ff281239eeefea4e9d2ffb9544b82d7c46f (diff) | |
drm/ast: Gen4: Fix open-coded register access
Replace all open-coded access to MCR and SCU registers in Gen4 with the
appropriate calls to ast_moutdwm() and ast_mindwm(). Use MCR and SCU
register constants. Name variables according to registers.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patch.msgid.link/20260327133532.79696-13-tzimmermann@suse.de
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions