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| author | Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com> | 2026-06-03 12:22:17 +0530 |
|---|---|---|
| committer | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2026-06-03 13:47:03 -0700 |
| commit | f22dbf90f011fa1ae0fe02841fb2676f87633783 (patch) | |
| tree | f7d21a044ef72b1d6bd4a75a726917574ef161ea /tools/perf/scripts/python/task-analyzer.py | |
| parent | 4b1ae138b0e103d753773956a84eebc2edbf62c4 (diff) | |
drm/xe: explicit TLB flush for context based tlb invalidation
In LR preempt-fence mode, on devices with context based
TLB Invalidation, rebind operations for VMAs require
an explicit invalidation request.
Request explicit TLB Invalidation in notifier path
and in PT path.
Userptr VMAs are excluded in PT path since the notifier path
already submits invalidation, preventing duplicate
requests for the same rebind window.
v2: Remove explicit TLB Invalidation in notifier path as
PT path is sufficient.
Refactor of above to remove exclusion of userptr VMAs n
PT path.- Thomas
v3: Knit-Remove unrelated change.-Thomas
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
Reviewed-by: Thomas Hellstrom <thomas.hellstrom@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patch.msgid.link/20260603065217.3131066-4-tilak.tirumalesh.tangudu@intel.com
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions